Production-ready flow for advanced customer designs

The Design Compiler Graphical synthesis tool underwent rigorous five nanometer enablement validation and has demonstrated correlated timing, area, power, and congestion to IC Compiler II place-and-route. Design Compiler Graphical five nanometer capabilities deliver improved performance, power, and area driven by new technology innovations, including enhancements to via-pillar optimisation, multibit banking, and pin-access optimisation.

Important to delivering the required design density are enhancements in IC Compiler II to handle complex, multi-variant and two-dimensional cell placement natively during optimisation while maximising downstream routability and overall design convergence.

Parametric on-chip variation (POCV) analysis in Synopsys' PrimeTime timing analysis and signoff solution has been enhanced to accurately capture increased non-linear variation due to process scaling and low-voltage operations commonly used to achieve energy efficiency. In addition, PrimeTime physically-aware ECO is expanded to support more complex layout rules for improved congestion, placement, and pin access awareness.

Suk Lee, TSMC senior director, Design Infrastructure Marketing Division, stated: "This five nanometer, EUV-enabled node is a core milestone for TSMC and continues to extend our leadership in the broader industry for best-in-class process technology offerings. We have worked closely with Synopsys on flow simplification and accelerated time-to-results to enable mutual customers to adopt this new process node using the Synopsys Design Platform. This collaboration has maximised process entitlement for high-performance computing and ultra-low power mobile applications, and we look forward to continuing this for our next-generation node."

Michael Jackson, Corporate Vice President of Marketing at Synopsys, added: "Early path-finding and extensive collaboration with TSMC has enabled mutual customers to take full advantage of the TSMC five nanometer process technology using the Synopsys Design Platform. Our joint commitment to this effort has accelerated customer access to the five nanometer process node, speeding the world's highest-density designs to production with best-in-class power, performance, and area."

Synopsys Design Platform technology files, libraries, and parasitic data are available from TSMC for the five nanometer technology process. Key products and features of the Synopsys Design Platform certified by TSMC for its five nanometer FinFET process include:

• IC Compiler II place-and-route: Fully automated, full-colour routing and extraction support, next-generation placement and legalisation technologies to mitigate cell footprint shrinks, and advanced legalisation and pin-access modelling for high design utilisation. 
• PrimeTime signoff timing: Advanced variation modelling for low voltages and enhanced ECO technologies with support for new physical design rules.
• PrimeTime PX power analysis: Advanced power modelling to accurately analyse leakage effects of ultra-high-density standard cell designs.
• StarRC signoff extraction: Advanced modelling to handle the complexity of five nanometer devices, as well as a common technology file for parasitic extraction consistency from synthesis to place-and-route to signoff.
• IC Validator physical signoff: Qualified DRC, LVS, and fill runsets developed natively, and released at the same time that TSMC released the design rules.
• HSPICE, CustomSim, and FineSim simulation solutions: FinFET device modelling with Monte Carlo feature support, and accurate circuit simulation results for analog, logic, high-frequency, and SRAM designs.
• CustomSim reliability analysis: Accurate dynamic transistor-level IR/EM analysis for five nanometer EM rules.
• Custom Compiler custom design: Support for new five nanometer design rules, colourings flow, poly track regions, and new MEOL connectivity requirements.
• NanoTime custom timing analysis: Runtime and memory optimisation for 5-nm devices, POCV analysis for FinFET stacks, and enhanced signal integrity analysis for custom logic, macros, and embedded SRAMs.
• ESP-CV custom functional verification: Transistor-level symbolic equivalence checking for SRAM, macros, and library cell designs.