Platform enables transition to 3D FinFET-based designs

Over 20 industry leaders worldwide have successfully completed more than 100 FinFET tapeouts using the platform.  Foundries including GLOBALFOUNDRIES, Intel Custom Foundry and Samsung have implemented test chip and production FinFET tapeouts with Galaxy Design Platform for mutual customers including Achronix, Global Unichip Corporation (GUC), HiSilicon Technologies, Marvell, Netronome, NVIDIA, Samsung and others, representing a broad spectrum of application markets, including consumer electronics, wireless, graphics, MPU and networking devices.

FinFET-based process nodes offer a number of advantages including greater density, lower power and higher performance. Innovative technologies in the Galaxy Design Platform implementation tools seamlessly handle the myriad design rules associated with the shift from planar to 3D transistors to enable these advantages.

Synopsys has engaged in comprehensive collaboration with foundry partners to ensure all the tools in the Galaxy Design Platform have been updated to support the process changes introduced by FinFET devices including multi-patterning and local interconnect structures. The updated tools include the Design Compiler synthesis solution, TetraMAX ATPG, IC Compiler and IC Compiler II place and route solutions, PrimeTime signoff solution, StarRC extraction, HSPICE, CustomSim and FineSim simulation products, Galaxy Custom Designer schematic, and Laker layout tools as well as IC Validator physical verification.

“Long-standing and close collaboration with foundries and end-users of FinFET technology has enabled Synopsys to reach this significant milestone,” said Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys. “Over the past few years, companies have deployed the Galaxy Design Platform for production of semiconductors using FinFET devices. Our customers require the highest performance and lowest power for their designs, which is driving their transition to FinFET. Designers can confidently use Galaxy tools for their FinFET designs and achieve superior quality of results.”

“We have selected the Galaxy Design Platform for all of our FinFET implementation because of the superior quality of results delivered by the platform,” said Yu Lin, Senior Director of Technology, Platform Engineering, HiSilicon Technologies. “A strong collaboration with Synopsys has enabled us to meet our production tapeout milestones for all Cortex-A Series designs in a timely and predictable manner. We are broadly deploying the platform to achieve superior results.”