Place & route solution enables tapeout of Toshiba's 40nm SoC

IC Compiler II is built on a multi-threaded infrastructure that is able to handle designs with more than 500 million instances while continuing to utilise industry-standard input and output formats, as well as familiar interfaces and process technology files. Leveraging this infrastructure, the place-and-route solution offers ultra-high capacity design planning, clock-building technology and patented global analytical optimisation, enabling enhanced area, timing and power QoR. These innovative technologies enable IC Compiler II to deliver five times faster runtime along with half the memory and half the iterations required to achieve target QoR, all together enabling a ten times boost in design throughput. 

"We are extremely impressed with the unprecedented runtime speedup and superior QoR delivered by IC Compiler II on this tapeout," said Mr. Kazunari Horikawa, Senior Manager, Design Technology Development Department, Mixed Signal IC Division, Toshiba. "The ultra-fast implementation turnaround times enabled daily iterations on this complex SoC, allowing us to exceed our QoR goals. We have released our IC Compiler II based design kit to commence standardisation on IC Compiler II to enable other critical designs within Toshiba to benefit from these game-changing capabilities."

"Toshiba joins the growing list of companies who are adopting IC Compiler II," commented Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys. "The successful tapeout of this highly complex SoC and Toshiba's decision to subsequently expand the usage to other programs with their design kit underscores the unique value IC Compiler II is delivering to a rapidly growing user base."