Multi-protocol IP reduces power and area by over 35%

24th May 2017

Synopsys Inc

Alice Matthews

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Suitable for high-performance computing applications including machine learning and artificial intelligence, Synopsys has announced its new DesignWare Multi-Protocol 25G PHY IP. The PHY IP gives designers the flexibility to efficiently integrate multiple protocols including PCI Express 4.0, 25G Ethernet, SATA and CCIX into system-on-chips (SoCs) targeting the 7 and 16nm FinFET processes.

The multi-protocol 25G PHY reduces power and area by more than 35% compared to the 16G PHY solution, incorporating optional power management features such as I/O supply under drive and decision feedback equalisation (DFE) bypass. In addition, the programmable continuous calibration and adoption (CCA) feature optimises performance across voltage and temperature variations, which is critical in harsh data centre environments. Designers can integrate the multi-protocol 25G PHY with Synopsys' digital controllers and verification IP for a complete, low latency, power-efficient IP solution that is compliant with the industry-standard protocol specifications.

"Globally, peak Internet traffic is projected to increase 4.6x from 2016 to 2020, a 36% CAGR, requiring semiconductors to incorporate new capabilities to meet high bandwidth demands of data centre SoCs. The average number of IP blocks in these SoCs was 151 in 2016 and is projected to grow to 246 by 2020," said Richard Wawrzyniak, Principal Analyst at Semico Research and Consulting Group. "Semico foresees the main enablers for high data rates to be high-speed SerDes solutions such as Synopsys' new optimised DesignWare Multi-Protocol 25G PHY IP."

Key features:

Flexible clock multiplier unit (CMU) including dual PLLs and dividers to support flexible multi-protocol configurations while transmitting high-quality data across lossy channels
Performance analogue front-end that incudes adaptive continuous time linear equaliser (CTLE), decision feedback equalisation (DFE) and feed forward equalisation (FFE) for signal integrity and jitter performance
Embedded bit error rate (BER) circuitry to efficiently evaluate channel quality, and on-die test features for testability and visibility into system performance, without requiring external test equipment

"The increase in global data traffic due to the growth of connected devices is requiring faster data transmission over the network," said John Koeter, Vice President of Marketing for IP at Synopsys. "The DesignWare Multi-Protocol 25G PHY addresses the high bandwidth and quality of service requirements for high-performance computing SoCs that require a wide range of interconnect protocols."