Multi-project wafer customers provided with configurable IP solutions

The automated flow allows complex CPU sub-systems to be delivered to customers in a matter of days. This sub-system can include single or multiple eSi-RISC processor cores with JTAG debug, and a range of peripherals and timers as well as encryption accelerator cores to enable secure boot and communication. The system is built around standard multi-layer AMBA AHB bus fabric generated as part of the automated flow.

Additional APB, AHB, AXI buses can be included to allow the easy integration of the customer’s own IP cores. This design flow allows EnSilica processor sub-systems to be delivered to customers well ahead of the first ASIC UltraShuttle-65 MPW run in October 2016.

Ian Lankshear, CEO of EnSilica, said he was extremely pleased to be an active and integral partner to BaySand in its new ASIC UltraShuttle-65 MPW program. “By supporting multiple projects customisable by four metal layers and facilitating access to deep sub-micron silicon by offering an affordable and reliable ASIC solution, the ASIC UltraShuttle-65 program redefines the traditional silicon shuttle concept offered by other foundries.”

With the support of a proven design flow and methodology that does not require any special EDA tools, expertise or licenses, the ASIC UltraShuttle-65 MPW program is structured to deliver high quality, verified and fully tested ASICs. The methodology is based on BaySand’s fully characterised standard cell library, coupled with EnSilica’s eSi-family of silicon proven IP and combined with BaySand’s RTL signoff design methodology that includes Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), full scan, JTAG, BIST and physical implementation. The ASIC UltraShuttle-65 MPW can also be used for FPGA to ASIC conversion minimising risk, reducing the cost and shortening the time-to-market.

EnSilica’s eSi-RISC is a family of highly configurable and low-power soft processor cores for embedded systems that scale across a wide range of applications and uniquely support both 16 32-bit configurations. The cores have been extensively silicon proven in a variety of ASIC technologies down to 28nm. The eSi-RISC family is fully supported by EnSilica’s extensive range of IP libraries comprising eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications solutions as well hardware accelerators.

“We are very excited to have EnSilica supporting our initiative to bridge the gap between ASIC designers and the 65nm ASIC implementation,” said Ehud Yuhjtman, BaySand’s EVP Marketing and Sales. “With EnSilica’s involvement in the ASIC UltraShuttle-65 program, our mutual customers now have the opportunity to implement a SoC with a full set of sophisticated IPs including RISC-based CPU, encryption and hardware accelerators.”