Management and analysis simulation made easier

The included solution provides designers with full access to the advanced features available in Synopsys SPICE and FastSPICE simulators and eliminates the need for third party environments. As an early collaboration customer, Samsung Electronics’ System LSI Business evaluated the new environment with FineSim SPICE and has deployed it to its analogue design community.

Advanced node designs must work across a wide range of voltages and operating conditions, and have many modes of operation. To verify circuits under various operating conditions, design teams are running thousands of simulations and need to sort through massive amounts of data. To address this growing complexity, Synopsys has developed a GUI-based transistor level simulation and analysis environment that is integrated with its circuit simulators and eliminates the need for any third party environment.

Key capabilities of the environment include:

• Netlist-based flow for direct import of SPICE, Verilog and DSPF.
• Unified set-up for corners, sweeps across multiple testbenches and Monte Carlo analysis.
• Advanced job distribution and monitoring for batch mode simulations.
• Integration with Synopsys’ Custom WaveView graphical waveform viewer for extensive post-processing of waveforms.
• Automated regression capability with industry standard TCL scripting language.
• Language sensitive text editor for netlist-based navigation, cross-probing and syntax checking.
• Advanced visual data navigation and data mining features such as charting, statistical analysis, histograms and scatterplots.
• Detailed report generation, including web-based HTML documentation.

“This upgrade to our circuit simulation portfolio provides a self-contained analogue verification environment that improves circuit verification productivity and obviates the need for third party tools,” said Antun Domic, Executive Vice President and General Manager at Synopsys. “Redefining what constitutes circuit simulation adds value to our customers’ investment in our products and validates our commitment to deliver innovative solutions to address their circuit verification needs.”

Synopsys will premiere a one hour webinar ‘Improving Analog Verification Productivity Using Synopsys' Simulation and Analysis Environment (SAE)’ on Wednesday, 17th February at 10:00a.m. PST. This webinar provides an introduction to SAE and its key capabilities for improving productivity and throughput. The webinar will be available for on-demand viewing for the remainder of 2016.