LPDDR4 VIP accelerates verification closure

Synopsys' 100% native SystemVerilog VIP for the JEDEC LPDDR4 memory protocol specification includes transactor and monitor functions to provide a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on LPDDR4-based designs. In addition to providing LPDDR protocol verification, the Synopsys LPDDR4 VIP can be dynamically configured to model any memory vendor component without the need to recompile, enabling SoC teams to rapidly verify the range of components that will be used with their SoCs.

Kevin Widmer, Vice President, Technical Marketing, SK hynix, comments: "LPDDR4 is an exciting step forward in technology providing lower power and higher performance, enabling the mobile industry to stay on the leading edge of the performance curve. The release of Synopsys memory VIP with advanced verification features devised for the LPDDR4 specification enables faster development of products and enables higher-confidence in compliance verification for SoCs and designs with memory interfaces."

Debashis Chowdhury, Vice President, R&D, Verification Group, Synopsys, comments: "We have collaborated extensively with leading-edge SoC design teams to address the increasingly demanding process of protocol compliance for on-chip buses, off-chip interfaces and memory. We continue to deliver solutions that enable designers to accelerate their SoC verification closure and decrease time to market. Synopsys LPDDR4 VIP provides SoC teams with the built-in protocol knowledge, features and methodology support to save time, increase design quality and meet project schedules."

Synopsys VIP for LPDDR4 is available today standalone and as part of the Synopsys VIP Library and the Verification Compiler product.  LPDDR4 VIP is also included as part of Synopsys' complete DesignWare IP solution for LPDDR4 that includes controllers, PHY and VIP.