Low power reference kit for design and verification

 The detailed low power flow and accompanying reference kit covers all aspects of a typical SoC design flow, methodically stepping through all phases from RTL creation through final signoff. It is specifically designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology by providing all design views with built-in templates and scripts spanning more than 15 Synopsys products.

The low power reference kit can also be used as an integrated learning vehicle for the complete Synopsys low power flow. Modular in nature, it easily helps with incremental adoption of a specific or broader-range of tools, allowing project teams to concentrate on particular functional areas such as verification or implementation.

The reference kit includes a user guide that provides step-by-step instructions for the individual tools used during various stages of a low power design flow.  

"Power efficiency is a key imperative in design where engineers are using complex and advanced strategies to minimize SoC power consumption," said Godwin Maben, Reference Kit Architect and Scientist for Synopsys' Design Group. "The Synopsys low power reference kit encapsulates the complex techniques in an easy to deploy, silicon-proven flow using market-leading implementation and verification tools from Synopsys." 

Key Synopsys products covered by the low power reference kit include:

• IC Compiler II place and route system.
• Design CompilerRTL synthesis product family.
• DFTMAX and TetraMAXII test solutions.
• Formality formal verification tool.
• PrimeTime and PrimeTime PX timing and power signoff.
• StarRC extraction solution.
• VCSnative low power simulation.
• Verdiautomated debug system.
• SpyGlassstatic verification tool.
• VC LP low power static verification.