Low-power IP enables designers to reduce design risk

DesignWare Logic Libraries give engineers the ability to optimise their entire SoC design for speed and energy efficiency by including nine-track high-density and 12-track high-speed libraries with long channels and power optimisation kits to reduce power consumption. High-speed, high-density and low-voltage DesignWare Embedded Memories offer multiple power management modes including light sleep, deep sleep and shutdown-with-retention to enable designers to meet aggressive power targets and extend the battery life of their products.

"The availability of DesignWare Logic Library and Embedded Memory IP on the Mie Fujitsu Semiconductor 40LP process enables our mutual customers to reduce design risk," said Masahiro Chijiiwa, Director and Corporate Executive Officer, Mie Fujitsu Semiconductor. "The combination of our 40LP process and Synopsys' comprehensive portfolio of logic libraries and embedded memories enables designers to speed SoC development and quickly ramp to volume production."

"As the leading supplier of physical IP, Synopsys provides designers with silicon-proven logic library and embedded memory IP that supports a range of process technologies for leading foundries," said John Koeter, Vice President of Marketing for IP and Prototyping, Synopsys. "By offering DesignWare Logic Library and Embedded Memory IP for Mie Fujitsu Semiconductor's 40LP process, Synopsys enables designers to incorporate necessary low-power features for longer battery life in their mobile and consumer products."