Low-power DRAM designs with higher density & performance

Synopsys' VIP for DDR4 3DS is natively integrated with its Verdi Protocol Analyzer, offering a graphical protocol-aware debug environment that synchronises memory transactions with signals. Complete with verification plans and built-in coverage, Synopsys' VIP for DDR4 3DS accelerates verification closure for designers of next-gen memory interfaces that require higher capacity and performance and reduced power to support enterprise computing devices, servers and data centres.

"The next generation of EZchip's multicore processors, the TILE-Mx, is optimised for high-performance networking applications and supports multiple DDR4 interfaces for up to 1TB of memory. A fundamental part of the new processor solution is high-performance and high-density DDR4 3DS LRDIMM," said Erez Shaizaf, Director, VLSI, EZchip Semiconductor. "Synopsys VIP for DDR4 3DS is easy to use and provides the pre-defined LRDIMM model with comprehensive checks and coverage. The VIP will enable us to close verification of the next-generation memory interfaces faster."

"As an active contributing member of the JEDEC, we have closely collaborated to develop DDR4 3DS VIP that allows leading-edge memory design teams to address the increasingly demanding process of protocol verification. The VIP accelerates verification closure and time-to-market," said Debashis Chowdhury, Vice President, R&D, Synopsys Verification Group. "The release of Synopsys' VIP for DDR4 3DS demonstrates the results of our continued collaboration with SoC market leaders to enable increased design quality and faster, more complete verification closure."

Synopsys VIP for DDR4 3DS is available today, as well as being included in the Synopsys VIP Library and the Verification Compiler products.