IP solution supports RAS features for cloud computing SoCs

Designers of enterprise systems require increasing levels of bandwidth and that is driving designers to adopt the latest versions of the 16GT/s PCIe 4.0 specification. Even while the PCIe 4.0 specification is under development, Synopsys performs extensive interoperability testing with ecosystem partners to help designers reduce design risk for their initial products with PCIe 4.0. 

The DesignWare Controller IP for PCIe 4.0 supports multiple lanes (x1 to x16) and multiple datapath widths for optimal configurations, as well as Native, ARM AMBA AXI-3 and AMBA AXI-4 interfaces for easy integration into SoCs. The DesignWare PHY IP for PCIe 4.0 supports full-featured bifurcation and aggregation, offering designers the flexibility either to configure the PHY macro into multiple individual links at 2.5, 5, 8 or 16GT/s, or to aggregate the PHY macro up to 16 lanes. Synopsys PCIe 4.0 Verification IP is based on a 100% SystemVerilog, UVM-based architecture with test suites delivered as source code to enable quick development of a verification environment to verify the proper integration and connection of the PCIe interface within the SoC.

"Our successful PCIe 4.0 system interoperability with Synopsys demonstrates the robustness of both the specification and our products," said Alon Webman, Vice President of Silicon Engineering, Mellanox Technologies. "The PCIe 4.0 specification, supported by industry leaders like Synopsys and Mellanox as well as the full PCI Express ecosystem, will support the requirements of enterprise applications to handle ever-increasing amounts of data."

"Teledyne-LeCroy works closely with Synopsys to ensure interoperability between our respective solutions and to ensure compliance to the latest PCIe specifications," commented John Wiedemeier, Product Marketing Manager, Teledyne-LeCroy. "By starting interoperability testing early in the specification development process and continuing through specification updates, Teledyne-LeCroy and Synopsys are giving designers confidence that the IP will work as expected, thereby reducing their design risk."

"RAS is growing in importance in high-performance cloud computing applications to ensure the data integrity of terabytes of data," said John Koeter, Vice President of Marketing, IP and Prototyping, Synopsys. "Synopsys continues to invest in PCIe IP to enable designers to integrate the latest versions of the PCIe specification and provide the RAS features needed for data-intensive SoCs."

The DesignWare Controller and Verification IP for PCIe 4.0 are available now. For availability information on the DesignWare PHY IP for PCIe 4.0, please contact Synopsys. DesignWare IP Prototyping Kits for PCI Express are also available now.

Synopsys will demonstrate its PCIe 4.0 IP solutions and interoperability with Mellanox at PCI-SIG Developers Conference 2015 in Santa Clara, CA from 23^rd to 24^th June.