Imec And Target Present Multi-Standard Low-Power LDPC Engine For Multi-Gbps Wireless Communication

This programmable LDPC engine is compliant with different standards such as 802.11ad (60GHz) and 802.11ac, and outperforms dedicated hard-wired implementations in throughput and energy efficiency.

“A strong ASIP design flow is critical to gain a competitive engineering advantage in cost, performance and power of reconfigurable radio architectures,” said Liesbet Van der Perre, Green Radio program director at imec. “Target Compiler Technologies offers a very compelling technology in this area. We are pleased to extend our licensing and R&D partnership with them, and we are looking forward to jointly develop new breakthroughs in digital architectures for next-generation mobile applications and technologies.”

Using Target’s IP Designer tool-suite for the design and programming of ASIPs, imec designed a multi-Gbps LDPC processor template that uses a programmable datapath architecture with parallel slices supporting instruction and data-level parallelism. The locality of reference imposed by the slices concept results in high energy efficiencies. The ASIP was validated for the 802.11ad (60GHz) standard in a commercial 40nm technology. Surpassing power, area and throughput of known dedicated fixed-function implementations, the multi-standard layered LDPC decoding engine achieved a throughput up to 7.6 Gbps at 3 iterations with a latency of less than 90 ns and a record energy efficiency of 4 pJ/bit/iteration in 40G TSMC technology. Moreover, owing to the instantaneous availability of an efficient software development environment, the ASIP methodology offers high productivity and easy instantiation to other multi-Gbps modes and standards like 802.11ac.

Gert Goossens, Target’s CEO, said: “The implementation by imec of this new flexible FEC architecture based on our IP Designer tool-suite proves that programmable ASIP solutions can compete with fixed-function hardwired IP blocks for advanced wireless standards, delivering superior performance results. IP Designer allows to quickly validate the impact of architectural changes on throughput, latency, silicon area and power consumption, thereby reducing the design risk. Additionally, ASIP implementations resolve issues with the instability of emerging standards and enable system-on-chip customers to include proprietary features in their chipsets. In recent years, Target Compiler’s IP Designer has been adopted by major industrial players to design their wireless modem solutions.”