LG Adopts In-Design Physical Verification with IC Compiler and IC Validator after Multiple Successful Tapeouts

In contrast to the older iterative approach of physical design followed by verification, the In-Design approach accelerated manufacturing compliance for LG Electronics by two weeks.

Competitive implementation of ARM processors in our designs is critical to market leadership and drives our platform strategy, said Dr. Woo-Hyun Paik, Research Fellow of SIC R&D Lab, at LG Electronics. We found IC Validator's In-Design approach to physical verification crucial to ensuring manufacturing compliance while honoring the performance, power and other constraints of complex, high-performance, energy-efficient processor design. In our recent tapeouts, we have successfully used key IC Validator capabilities, including timing-aware fill and automatic design rule checks (DRC) repair, enabling us to achieve manufacturing compliance ahead of schedule.

With feature geometries shrinking, the number and complexity of DRC needed to achieve manufacturing compliance has grown exponentially. This has rendered the traditional physical verification approach, which relies on modifications to design after the GDSII has been generated, disadvantageous. The traditional approach can create multiple discover-then-fix iterations and can lead to suboptimal results. Examples are metal-fill insertion and design-rule checking, which today are universally mandated manufacturability compliance steps. The traditional approach would require physical designers to stream out the timing-closed, post-fill design for signoff validation and then stream it back in to fix any errors, setting the stage for multiple iterations. The same concerns are also applicable to the traditional approach to generalized design rule checking after the design has been completed, potentially leading to late-stage surprises and ensuing expensive iterations that can significantly impact tapeout schedules.

In-Design physical verification with IC Validator addresses these manufacturability challenges within the IC Compiler environment. The well-integrated flow enables an optimized metal-fill flow that is not only timing aware with sign-off quality, but also avoids expensive and error prone stream-outs and stream-ins. For design rule checking, the In-Design flow uses foundry-qualified rule decks to flag errors in the layout and also drive automated repair, potentially saving days compared to the traditional approach of post-design validation and subsequent manual repairs.

In-Design physical verification with IC Compiler and IC Validator exemplifies how smart technology integration of the right platforms offers a high-efficiency turnkey solution to enable designers to accelerate time to tapeout, said Antun Domic, senior vice president and general manager of Synopsys' implementation group. By adopting In-Design physical verification with IC Compiler and IC Validator, LG Electronics is taking advantage of Synopsys' platform integration that offers the optimal solution for high-performance, energy-efficient ARM processor implementation.