el="nofollow" href=http://synopsys.com/Tools/Implementation/PhysicalVerification/Pages/ICValidator-ds.aspx target=blank>IC Validator 2012.06 continues to build on Synopsys' approach of speeding design closure through In-Design physical verification with Synopsys' IC Compiler place and route solution, enabling place-and-route engineers to eliminate late stage surprises and manual repairs. New additions to the In-Design flow, targeted for 20nm and below, include DPT and pattern matching technology. This latest release of IC Validator also offers a significant performance boost for verifying large and complex 20-nm designs. By maximizing the utilization of mainstream computing hardware through innovative techniques, IC Validator can enable engineers to parallelize design rule checks on 64 processing cores and beyond, thereby significantly reducing verification turnaround time for these advanced process nodes.

To address the complexities of 20nm process, we are actively expanding the use of In-Design Physical verification with IC Compiler and IC Validator for our new designs, said Kyu-Myung Choi, senior vice president of Infrastructure Design Centre, Samsung Electronics.

Enabling Physical Verification at 20nm and Below

To address the stringent manufacturing requirements of 20-nm design, IC Validator 2012.06 introduces several new advances in process modelling technology:

•Double Patterning: The limitations of current lithographic technology require layout to be split into two masks of alternating structures. IC Validator features a fast and accurate, native decomposition (colouring) engine. IC Validator can perform decomposition checks during design and can also drive automatic fixing of violations with IC Compiler via the In-Design technology. IC Validator can also perform the final signoff quality check alongside the final design rule check.

•Pattern Matching: Occasionally layout patterns can generate lithography hotspots, leading to accidental open or short connections. IC Validator's patented pattern-matching technology augments DRC with intuitive 2D multi-shape pattern analysis for ultra-fast detection of manufacturing hotspots. It can also drive automatic fixing of these hotspots with IC Compiler. Leading manufacturers will thus be able to achieve better process margins and higher yields for the 20-nm process node.

Improving Design Turnaround Time

IC Validator is being broadly used by design teams for In-Design physical verification with IC Compiler. This release complements IC Compiler 2012.06, allowing users to benefit from 2X faster ECO and automatic design repair flows. New additions to In-Design technology also make it possible for designers to perform layout enhancement for yield natively within IC Compiler, streamlining the design flow and eliminating wasteful iterations.

In addition to being used for In-Design verification, IC Validator is also fully qualified for physical signoff at leading foundries across a broad range of process technologies. IC Validator 2012.06 deploys a range of distributed multiprocessing techniques to achieve optimal utilization of available hardware. These technologies, including multi-threading, on-demand load balancing and memory-aware scheduling, have demonstrated scalability to 64 cores and beyond. With this release, customers designing at advanced process nodes can now benefit from a significant productivity boost and faster turnaround times.

IC Validator 2012.06 is the most noteworthy release for our physical verification product line to date, said Antun Domic, senior vice president and general manager of Synopsys' implementation group. Beyond enabling verification of the highly complex 20-nanometer process technology node at Samsung and other leading foundries with a multitude of new technologies, we have added significant improvements in runtime, scalability and In-Design productivity that will benefit our entire customer base.