Design

IC compiler place & route increases designer productivity

3rd June 2015
Barney Scott
0

Synopsys has announced that STMicroelectronics has taped out its latest Fully Depleted Silicon On Insulator (FD-SOI) SoC using Synopsys' IC Compiler II place and route solution. Collaborating closely with Synopsys, ST used the tool to complete more than half of the chip, achieving higher designer productivity and better device performance.

Unveiled in 2014, IC Compiler II is the successor to IC Compiler, the industry's current leading place and route solution for advanced design at established and emerging nodes. Driven by the FD-SOI tapeout success, ST is actively engaged in broadening the usage of IC Compiler II.

IC Compiler II is a production-ready, full-featured place and route system architected from the ground-up to realise an order-of-magnitude leap forward in designer productivity. It is built on a multi-threaded infrastructure able to handle designs with more than 500 million instances while continuing to utilise industry-standard input and output formats, as well as familiar interfaces and process technology files.

Leveraging this new infrastructure, IC Compiler II offers ultra-high-capacity design planning, unique new clock-building technology and patented global analytical optimisation, enabling enhanced Quality of Results (QoR) in area, timing and power. Representing years of engineering innovation and featuring several dozen new patents, these innovative technologies enable IC Compiler II to deliver five times faster runtime along with half the memory and half the iterations required to achieve target QoR – all together enabling a tenfold boost in design throughput. This level of speed-up is already enabling game-changing possibilities for IC Compiler II users and is continuing to transform how physical design is done.

"Looking back, we can safely say it would have been exceedingly difficult to do a chip of this magnitude without IC Compiler II," said Thierry Bauchon, R&D Director at STMicroelectronics. "Our experience proved the promise we saw early in the design with ten times faster design exploration and five times faster implementation, enabling us to refine floorplans, up-size physical partitions and achieve faster clock speeds on this tapeout."

"Over the years ST has been a steadfast partner helping us develop and deploy advanced design technology, and that has continued with our very latest offering, IC Compiler II," said Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys.  "The successful tapeout underscores the unique value IC Compiler II is delivering to a rapidly growing user base."

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