Design

IC Compiler II is certified on 10nm FinFET process

17th September 2015
Nat Bowers
0

TSMC has certified Synopsys' IC Compiler II place and route product for V0.9 of 10nm FinFET (N10FF) process technology and are on track to work towards V1.0 completion in Q4, 2015. IC Compiler II is the successor to IC Compiler, the place and route solution for advanced designs, delivering an improvement in throughput while achieving quality-of-results that meets TSMC's certification requirements.

IC Compiler II is a place and route system built from the ground up to deliver improvement in design turnaround. Its new, highly innovative technology infrastructure includes data model, library and core engine advances that maximise multi-core and multi-machine scalability. Patented adaptive abstraction and compact data encapsulation technologies deliver capacity for large scale design planning tasks while concurrently achieving faster implementation.

With QoR being a key focus during its development, IC Compiler II features an analytical physical synthesis engine, variation-tolerant clock-building techniques, and solver-driven post-route optimisation, which together deliver standard-setting timing, area and power benefits. Balancing innovation with strategic reuse of technologies in IC Compiler, IC Compiler II deploys the Zroute router and linear-gradient placer. These components enable day-one availability of technology files, along with a solid foundation to meet the stringent TSMC 10nm requirements, including: full colouring flow enablement; vertically-constrained placement; layer-based optimisation; low-Vdd timing-closure; and signal electromigration.

Bijan Kiani, Vice President of Marketing, Design Group, Synopsys, commented: "TSMC continues to push the limits of physics to enable faster, smaller and more energy-efficient silicon solutions, it is imperative that we work closely with them to accelerate design enablement. Through our partnership with TSMC on its 10nm process, we are ensuring that our mutual customers are successful at bringing innovative and exciting products to market at the new node faster than ever before."

Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC, said: "10nm is TSMC's next-gen FinFET process that delivers significant power, performance and area benefits across a broad range of design types and styles for the most demanding SoC applications. Through close collaboration with Synopsys, and our rigorous testing and certification of IC Compiler II, we are able to provide designers with a high-quality design enablement solution."

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