Hierarchical timing reuse reduces schedule-risk

13th December 2016

Synopsys Inc

Daisy Stapley-Bunten

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The 2^nd gen technology that enables semiconductor design teams to adopt a smarter, more efficient hierarchical approach to Static Timing Analysis (STA) for timing closure and signoff across all design sizes and levels of complexity has been announced by Synopsys.

Built on proven PrimeTime HyperScale hierarchical STA technology and included in the 2016.12 release of the PrimeTime static timing analysis tool, this capability automates partitioning and distribution of full-chip analysis across a company's private compute cloud, reducing costs and time.

"When we brought the first generation PrimeTime HyperScale technology to our early adopters, it revolutionised the way design teams completed timing closure and signoff on the largest and most complex chips," said Robert Hoogenstryd, Senior Director of marketing for design analysis and signoff tools at Synopsys. "Our second generation provides additional automation and flexibility, allowing more design teams the opportunity to adopt smarter hierarchical signoff flows while maintaining the gold standard accuracy they expect from PrimeTime."

Flexible Methodology with Proven Hierarchical Technology HyperScale has been used for static timing analysis on more than 40 of the largest and most complex designs at more than 15 different companies over the last 5 years. These tapeouts include complex graphics, high-performance computing, low-power mobile, and reliable automotive designs.

The 2^nd gen of PrimeTime HyperScale technology allows users to easily migrate from flat design analysis to hierarchical block-level analysis and full-chip distributed timing analysis, using mainstream compute resources available in private computing clouds. The hierarchical methodology supports both top-down and bottom-up flows, with state-of-the-art, timing-accurate context generation. This enables HyperScale block-level model analysis to be re-used throughout the flow, instead of re-analysing the same blocks over and over at each level. The 5–10x performance and memory improvements reduce both compute resource cost and schedule risk, for current and future designs.

Market-leading companies who have deployed HyperScale for use in their signoff and tapeout flows include Broadcom, Juniper Networks, MediaTek, Renesas Electronics and Samsung Electronics Company.