SMIC and Synopsys Extend 40nm Low Power Capabilities with Reference Flow 5.0

The reference flow is the result of collaboration between SMIC and Synopsys Professional Services, leveraging Synopsys' experience and expertise in advanced chip design methodologies. The reference flow features new high-performance design techniques, including automated clock mesh synthesis, to increase performance and responsiveness of a system on chip (SoC), plus a gate array engineering change order (ECO) flow that allows a designer to quickly achieve design closure without having to start from scratch with a redesign. The reference flow also includes support for low power techniques such as power-aware clock tree synthesis, power gating and physical optimization, driven by the IEEE 1801 low power design intent standard.

Designers require a reference flow that addresses both high-performance and low power requirements, said Tianshen Tang, SMIC's vice president of design service. With the release of SMIC-Synopsys Reference Flow 5.0, we are enabling IC designers to accelerate their designs into manufacturing through the combination of SMIC's 40nm process technology and Synopsys' technology-leading design solutions.

Customers are looking for tools and methodologies that allow them to deliver designs that meet their unique performance goals and requirements, said Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys. Through our collaboration with SMIC, we are able to provide our mutual customers a proven reference flow and immediate access to both high-performance and low power design solutions tailored for SMIC's 40-nanometer low power process.

Availability
The SMIC-Synopsys Reference Flow 5.0 is available now.