Synopsys unveil interface IP for TSMC 20SoC process

24th September 2013

Synopsys Inc

Nat Bowers

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Synopsys announce the availability of a range of DesignWare Interface IP on TSMC's 20-nanometer system-on-chip process. The silicon-proven Synopsys DesignWare USB, DDR, PCI Express and MIPI PHY IP on TSMC's 20SoC process reduces risk for designers who need to implement the latest interface IP standards in their SoCs and want to take advantage of 25 percent lower power consumption or a 30 percent performance improvement offered by TSMC's 20SoC process compared to TSMC's 28-nm process.

The DesignWare IP portfolio is designed to achieve high yield by meeting the requirements of advanced manufacturing design, such as adhering to double patterning layout rules.

Suk Lee, TSMC senior director, design infrastructure marketing division, comments: "TSMC and Synopsys have a long history of collaboration on leading-edge process technology migration, delivering high-quality, proven IP that helps our mutual customers speed their time to volume production. The availability of Synopsys' high-quality IP portfolio for our 20SoC customers provides a low-risk path to implementing proven IP while reducing SoC power consumption."

As designs migrate to smaller process nodes, such as 20-nm and 16-nm FinFET, the technology challenges to extend Moore's Law become increasingly complex. TSMC has implemented double patterning mask technology on its 20SoC process utilizing two photo masks, each with half of a pattern, to enable printing of images below the node's minimum spacing design rules. Synopsys' development of DesignWare IP at 20-nm focused on minimizing yield and manufacturability issues while adhering to the standards' specifications, as well as TSMC's advanced layout and design rules for manufacturability with double patterning technology.

"As the leading provider of physical IP with more than 80 test chip tape-outs in 20- and 28-nm, Synopsys is focused on developing IP in the most advanced process nodes to help designers take full advantage of the processes speed and power characteristics while implementing high-quality, proven IP. By offering a broad portfolio of IP for the 20-nm process, Synopsys enables designers to more easily meet their goals of creating differentiated products with less risk and faster time to volume production, while also reducing the risks associated with moving to the 16-nm FinFET process," commented John Koeter, vice president of marketing for IP and systems at Synopsys.

The Synopsys DesignWare USB 2.0 PHY, USB 3.0 PHY, DDR4 multiPHY, PCI Express 2.0 PHY, and MIPI D-PHY for the TSMC 20SoC process are available now.