DesignWare interface IP in development for TSMC 7nm process

The collaboration extends Synopsys' long history of successful IP development on TSMC advanced FinFET processes for high-performance, low-power SoCs.

"TSMC and Synopsys have a long track record of successful collaboration on advanced FinFET processes, providing our mutual customers with a low-risk path to integrating a broad portfolio of high-quality, silicon-proven IP into their SoCs," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "Achieving multiple customer tapeouts of Synopsys DesignWare IP on TSMC's 7nm process demonstrates the benefits of our collaboration and gives designers confidence that they will meet their power, performance and area targets while accelerating their time to market."

"As a leading provider of physical IP, Synopsys continues to provide early access to IP in the most advanced process technologies, helping designers incorporate necessary functionality and accelerate their design schedules," said John Koeter, Vice President of marketing for IP and prototyping at Synopsys. "With multiple customer tapeouts of DesignWare IP for TSMC's 7-nm process, Synopsys enables designers to reduce integration risk and differentiate their products with this latest technology."