Design solutions enable a premium mobile experience

Based on the results of previous collaborations, the reference implementation for the Cortex-A72 core takes advantage of ARM POP IP in 16nm FinFET Plus process, Synopsys HPC methodology, and the latest tools and features in the Galaxy Design Platform. To achieve up to 2.5GHz performance in a mobile computing power envelope, the reference implementation includes support for Synopsys' Design Compiler Graphical tool for RTL synthesis, IC Compiler and IC Compiler II for place-and-route, and PrimeTime solution for signoff and physical ECO. In addition, the reference implementation is compatible with the Lynx Design System. Synopsys technology key to achieving this performance and power level includes: physical guidance for a predictable implementation flow, concurrent clock and data optimisation for a boost in frequency, advanced clock gating, low-power clock tree synthesis and multi-bit register optimisation for dynamic power savings, and signoff leakage recovery for further power reduction.

IC Compiler II is Synopsys' latest offering in place-and-route and is a full-featured, production-ready netlist-to-GDSII implementation system, delivering the highest throughput and productivity along with the best quality of results. Developed from the ground up to deliver a leap forward in productivity, IC Compiler II is built on a highly efficient, multi-everything infrastructure and offers ultra-high capacity design planning, unique clock-building technology and advanced global analytical closure techniques. These technologies enable IC Compiler II to deliver a 5X speed-up in implementation runtime along with half the iterations required to achieve target performance, together providing a 10X boost in throughput.

Early adopters of ARM's new suite of IP for a premium mobile experience, which includes the ARM Cortex-A72 processor, CoreLink CCI-500 interconnect, Mali-T880 GPU, Mali-V550 video processor and Mali-DP500 display processor, have been successfully using Synopsys tools and methodology to design and verify their initial designs. Building on previous collaborations to enable ARMv8-A based processor and advanced Mali GPU designs as well as the new reference implementation for the Cortex-A72 core, Synopsys and ARM are collaborating to extend these solutions across the IP suite. These extensions include: optimised implementation with the Galaxy Design Platform, including IC Compiler II; virtual prototyping with virtualiser development kits for ARM v8-A based cores; optimised simulation, formal verification, advanced debug, verification methodology, as well as a next-gen verification IP, Verification Compiler product and ZeBu solution for emulation; HAPS FPGA-based prototyping systems; and a full chip design environment with the Lynx Design System. In addition, Synopsys’ Core Optimization Services have extensive experience helping designers optimise their CPU and GPU cores for performance, power and area.

"We have collaborated with Synopsys to ensure our mutual customers can bring innovative products to market quickly while meeting their performance, power and area targets," said Noel Hurley, General Manager, CPU Group, ARM. "Our collaboration to create an optimised reference implementation with Synopsys IC Compiler II for the ARM Cortex-A72 processor will help designers take advantage of the latest technology to efficiently create products that deliver a premium mobile experience."

"This collaboration with ARM brings the power of our place-and-route solution to Cortex-A72 processor based designs," said Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys.