Design compiler graphical solution improves performance

"As exciting infotainment and safety options become significant criteria in the purchase of new products, our customers are looking to Renesas to deliver higher performance, energy-efficient products to market," said Tatsuji Kagatani, Manager of Design Automation Department, Renesas System Design. "Design Compiler Graphical's significant area and routing congestion reduction, combined with IC Compiler for place and route, enable our design teams to achieve faster timing and smaller area. We have widely deployed Design Compiler Graphical for our products currently using our 40nm process."

Design Compiler Graphical addresses challenging requirements, such as performance, area, power and congestion, at all process nodes. It provides IC designers with visualisation of congested circuit regions and performs automated synthesis optimisations to minimise congestion in these areas. Optimisation technologies monotonically reduce design area and leakage power by an average of 20% while maintaining timing QoR. Design Compiler Graphical shares physical technologies with IC Compiler and IC Compiler II place-and-route solutions to deliver highly correlated results for timing, area, power and routability, reducing design iterations and shaving critical schedule time.

"In the automotive market that Renesas serves, performance, low power consumption and cost-effectiveness are essential goals for their designers," said Bijan Kiani, Vice President of Marketing, Synopsys' Design Group. "Design Compiler Graphical's advanced optimisation technologies and tight links with IC Compiler enable Renesas to deliver differentiated, high-performance products to market quickly."