DDR performance analysis tool is ten times quicker than RTL analysis

With the graphical simulation and analysis provided by DDR Explorer, designers can quickly select the right memory type for the lowest BOM cost and system power. DDR Explorer supports all of the industry standard DRAM interfaces for mobile and enterprise applications, including LPDDR2, LPDDR3, DDR2, DDR3 and DDR4.

DDR Explorer integrates a transaction-level architecture model of the DesignWare DDR Enhanced Universal Memory Controller with a graphical simulation and analysis environment that enables designers to define, run and analyse hundreds of scenarios to identify the best memory controller configuration.

RTL-based performance checking, while required for final validation, typically has longer turnaround times and limits the practical number of design explorations during a project to fewer than 25. DDR Explorer enables thorough performance and power sensitivity analysis for over 250 simulations in the same amount of time.

By identifying heavy traffic conditions and bottlenecks, designers can explore the DDR memory controller parameter configurations and register settings to optimise the DDR memory performance. This results in up to 20% greater memory efficiency, lower power consumption and lower memory cost, without sacrificing other memory performance requirements. The optimised configuration from DDR Explorer is used for DDR memory controller RTL IP configuration and performance validation, speeding the implementation and verification of the IP.

"With DDR Explorer, designers can rapidly configure, simulate and analyse the DDR memory controller and PHY subsystem," said John Koeter, Vice President of Marketing, IP and Prototyping, Synopsys. "DDR Explorer enables designers to significantly reduce the effort of integrating DesignWare DDR Enhanced Universal Memory Controller and PHY IP into their SoCs for faster time-to-market."

DesignWare DDR Explorer is available now.