Collaboration delivers design flow for packaging technologies

This enables customer deployments for high-performance, high-connectivity multi-die technology in mobile computing, network communication, consumer, and automotive electronics applications.

The platform-wide Synopsys solution includes multi-die and interposer layout capture, physical floorplanning, and implementation, as well as parasitic extraction and timing analysis coupled with physical verification. Key products and features of the Synopsys Design Platform supporting TSMC's advanced WoW and CoWoS packaging technologies include:

• IC Compiler II place-and-route: Supports multi-die floorplanning and implementation, including interposer and 3D stack-die generation, TSV placement and connectivity assignment, orthogonal multi-layer, 45° single-layer, and interface inter-die block generation for inter-die extraction and checking. 
• StarRC extraction: Supports modelling of TSV and backside RDL metal extraction, silicon interposer extraction, and inter-die coupling capacitance extraction. 
• IC Validator: Supports full-system DRC and LVS verification, inter-die DRC, and LVS checking of inter-die interface. 
• PrimeTime signoff analysis: Full-system static timing analysis, supports multi-die static timing analysis (STA).

Suk Lee, TSMC senior director, Design Infrastructure Marketing Division, said: "High-performance advanced 3D silicon fabrication and wafer stacking technologies require new EDA features and flows to support the corresponding increase in design and verification complexity. We extend our collaboration with Synopsys to deliver design solutions for TSMC's CoWoS and WoW advanced packaging technologies. We look forward to our mutual customers benefiting from the enabled design solutions, boosting designer productivity and accelerating time-to-market."

Michael Jackson, Corporate Vice President of Marketing and Business Development for Synopsys' Design Group, added: "Built through deep collaboration, the design solution and reference flow for TSMC's WoW and CoWoS chip integration solutions will enable our mutual customers to achieve optimal quality of results. The Synopsys Design Platform and methodologies will allow designers to confidently meet their schedules for cost-effective, high-performance, and low-power multi-die solutions."

Synopsys jointly highlighted the advances and collaborations of TSMC 2.5D and 3D technologies in a paper titled ‘Onwards and Upwards: How Xilinx is Leveraging TSMC's Latest Integration and Packaging Technologies with Synopsys' Platform-wide Solution for next-generation Designs’ at the TSMC Open Innovation Platform (OIP) Ecosystem Forum on October 3rd, 2018 in Santa Clara, California.