Breakthrough doubles single & multi-core speed-up

The CustomSim mixed-signal solution in VCS AMS has been extended to support SystemVerilog Real Number Models (RNM) for AMS regression methodology and UPF for low-power verification.

The CustomSim FastSPICE solution has consistently delivered higher performance to the design community each year. As design complexity increases due to advanced nodes and the prevalence of mixed-signal IP, significantly more performance and capacity is needed to quickly and accurately verify these designs. While multi-core simulation has been available for some time, traditional FastSPICE simulators have been unable to consistently deliver scalable multi-core performance beyond a small subset of design types. As a result, design teams are either forced to either sacrifice accuracy for performance and risk missing costly bugs in their designs, or lengthen project schedules to meet verification goals.

To address these challenges, CustomSim 2015.06 delivers advances in its multi-core technologies that enable double performance on four cores across a wide range of design types without sacrificing accuracy.

Post-layout simulation complexity and element counts for advanced-node designs have increased significantly. For example, the coupling effects between parasitic capacitance can no longer be ignored. This makes traditional FastSPICE partitioning algorithms ineffective, as they can no longer maintain the required accuracy. CustomSim 2015.06 debuts multi-level partitioning technology that efficiently solves this problem by maximising multi-rate simulation to deliver doubled performance on four cores while maintaining accuracy.

CustomSim 2015.06 uses an intelligent multi-core simulation scheduler that explores parallel activities among all circuit partitions to maximise multi-core scalability across a broad range of circuit types, including SRAM, analogue and mixed-signal designs. Additionally, CustomSim 2015.06 enhances the VCS AMS solution for mixed-signal verification with support for UPF for low-power designs and Real Number Modeling with SystemVerilog nettype.

"CustomSim is the reference FastSPICE simulator for BCD technology in the mixed-signal verification flow at STMicroelectronics," said Pier Luigi Rolandi, Design Enablement Director, Technology R&D, Sense, Power and Automotive, STMicroelectronics. "With the BCD option in CustomSim, we're seeing an average of twice improved performance in single-core and up to an additional doubling of performance on four cores. This performance gain allows us to accelerate the verification of our ICs in smart power technologies for automotive and industrial applications."

"As the leading provider of FastSPICE circuit simulation solutions, we have a solid track record of delivering innovative, best-in-class technologies to designers over the last 15-plus years," said Antun Domic, Executive Vice President and General Manager, Design Group, Synopsys. "Our early CustomSim users have seen two times throughput improvement using the CustomSim 2015.06 release. These results enable designers to produce more competitive products quickly."