Blue Pearl Software Announces Support for Synopsys Synplify Pro Design Flow

“Our collaboration with Synopsys resulted in an optimized flow that works with Synplify Pro FPGA synthesis software,” said Shakeel Jeeawoody, director of product marketing at Blue Pearl. “VHDL and SystemVerilog designers are now able to automatically generate an exhaustive set of constraints that address false and multi-cycle paths and that work with Synopsys’ leading synthesis flow.”



Blue Pearl Software Suite offers comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic Synopsys Design Constraints (SDC) generation for FPGA, ASIC and SOC designs. Its visualization and validation technology gives users immediate feedback for validating automatically generated pre-synthesis longest paths and SDC timing constraints.



Last month, Blue Pearl Software announced Release 6.0 of its Blue Pearl Software Suite with capabilities that support FPGA designers.



Price and Availability

The Blue Pearl Software Suite for FPGA design with Synplify Pro is available now.