ATPG solution reduces pattern count up to 50%

To address these needs, and following a thorough evaluation demonstrating up to 50% reduction in pattern count, significantly faster runtime and advanced power-aware features, Toshiba is planning to deploy TetraMAX II for their latest consumer electronics SoC design. Toshiba will be sharing their experience with TetraMAX II at the Synopsys Users Group (SNUG) India conference, opening 13^th July at the Leela Palace Hotel in Bangalore.

"Long ATPG runtimes and increasing test pattern counts are becoming bigger challenges on our large-scale SoC designs. Test pattern reduction within a short runtime is required to minimise test cost while maintaining the quality of test." said Kazunari Horikawa, Senior Manager at Toshiba's Design Technology Development Dept. "We have been collaborating with Synopsys, and confirmed through an evaluation that TetraMAX II shortens ATPG execution time and reduces the number of test patterns by up to 50% while maintaining the quality of test. We are planning to adopt TetraMAX II for our upcoming SoC designs and believe TetraMAX II will further reduce test cost with its strong roadmap."

"Synopsys is committed to addressing the evolving test requirements for designers worldwide " said Antun Domic, Executive Vice President and General Manager for Synopsys' Design Group. "Our recent collaboration with Toshiba demonstrates our continuous innovation and investment in new test technologies that addresses our customers' need for shorter manufacturing test time and faster ATPG while their designs complexity continues to grow."