ATPG engines speed test generation for SoC designs

To meet these challenges, STMicroelectronics requires fast turn-around time (TAT) for generating high-quality manufacturing test patterns. Following an evaluation using a multi-million-gate FD-SOI SoC design, TetraMAX II demonstrated an order of magnitude speedup in runtime and significant test-pattern-count reduction without impacting test coverage. As a result, STMicroelectronics is deploying TetraMAX II in their standard SoC design flow.

"Over the past several years, we have collaborated with Synopsys to address the growing manufacturing-test challenges of increasing complexity and manufacturing test costs in combination with requirements for higher quality and faster TAT," said Roberto Mattiuzzo, SoC integration and DFT methodologies manager in STMicroelectronics' Digital and Mixed Processes ASIC division. "During our evaluation on a high-density FD-SOI chip, TetraMAX II produced test patterns an order of magnitude faster while significantly reducing the number of patterns without any coverage loss. With these results, we are confidently testing first-silicon samples earlier and reducing tester time, too."

"Customers such as STMicroelectronics rely on Synopsys' test solution to ensure the best combination of fast TAT and low test costs with high quality," said Antun Domic, Executive Vice President and General Manager for Synopsys' Design Group. "Our long-term collaboration with ST continues to go from strength to strength. With the latest results from their TetraMAX II evaluation, we are demonstrating yet again our commitment to deliver continuous innovations in ATPG and related technologies to address our customers' manufacturing test challenges."