Advanced system-level capabilities in next-gen VC Verification IP

The expanded capabilities of Synopsys Verification IP include system level test-suites, a system monitor, protocol-aware debug and performance analysis. With the growth of cache-coherent designs, checkers and performance analysis are required. The system-level capabilities of Synopsys VIP enable SoC teams to further accelerate time to first test and improve overall verification productivity.

"ARM and Synopsys have a long history of successful R&D collaboration on leading-edge verification products, including AMBA protocols," said Andy Nightingale, Vice President of system IP marketing, systems and software group, ARM. "By adding system-level cache coherency VIP to support AMBA protocols, Synopsys is enabling our mutual customers to meet their aggressive targets and quickly bring innovative products to market."

Synopsys VIP features SystemVerilog source code test-suites, which include system-level coverage for accelerated verification closure. The VIP now also offers performance measurement metrics for in-depth analysis of throughput, latency and bottlenecks across cache coherent ports. Synopsys VIP also features system monitors, which interact with other VIP to ensure cache coherency across the system, accurate protocol behavior and data integrity.

Synopsys VIP is architected natively in SystemVerilog and UVM, is easy to use and can be integrated, configured and customised with minimal effort. It also supports native integration with Synopsys' Verdi Protocol Analyzer, a graphical protocol-aware debug solution. As a result, Verdi Protocol Analyser synchronises high-level transactions to low-level signal activity across every layer of the AMBA protocol and custom cache coherent interconnects, providing system level debug support.

Synopsys also announced availability of verification IP for AMBA 5 AHB5 protocol. The ARM AMBA 5 AHB5 protocol is an update to the widely adopted AMBA 3 AHB-Lite specification, enabling high-performance multi-master systems with support for exclusive transfers and additional memory attributes for seamless cache integration. The AHB5 protocol also enables closer alignment with the AMBA 4 AXI protocol, enabling easier integration of AXI and AHB5 systems. AHB5 also adds support for secure/non-secure signaling.

"We have collaborated closely with ARM in creating Synopsys VIP for system-level verification of AMBA protocols, helping leading-edge SoC design teams address the increasing complexity of coherency verification," said Debashis Chowdhury, Vice President of R&D, Synopsys Verification Group. "Our next-gen VIP helps designers accelerate verification closure and time to market as well as increase design quality."