Accelerating the SoC design cycle

To deliver competitive, cost effective COT design services to its customers, design implementation turnaround time (TAT) and predictability are key for AAI. To help meet these goals, AAI has deployed a fast turnaround implementation flow that includes early RTL analysis to identify and remove routing congestion with Design Compiler Graphical, followed by physical guidance to the IC Compiler II place-and-route solution. In addition, AAI uses advanced low power and design-for-test techniques within this flow. As a result, AAI achieves rapid turnaround for its SoC designs, saving an average of two to three weeks in their overall RTL-to-GDSII schedule.

“Improving the RTL-to-GDSII schedule of our COT design services is a critical goal to enable the success of our fabless and system design customers,” said Pavel Vilk, Engineering Director at AAI. “Design Compiler Graphical enables our design team to identify and remove routing congestion early in the flow and, with physical guidance to IC Compiler II, it enables us to speed-up the critical physical place-and-route and final design closure phases.

“Among the many benefits of using Design Compiler Graphical, our engineers like the ability to pinpoint specific RTL source code that causes congestion, especially in our larger blocks of over three million instances, so they can make fixes quickly before moving forward with place-and-route. As a result of our successful deployment experience with typical schedule savings of two to three weeks, we have standardised on Design Compiler Graphical for all our designs and are considering further flow improvements with close collaboration with Synopsys.”

Highlights of the latest release of Design Compiler, 2016.03, include:

• 25% faster run-time enabling the synthesis of designs as large as five million instances in hours vs. days.
• Ten percent reduction in total negative slack (TNS) for faster design closure.
• Tighter timing correlation for designs at 16-nanometer and 10-nanometer due to improved local timing delay estimates for complex floorplans, automatic estimation of via resistance based on process technology and layer promotion of up to 15 layers.
• Congestion reduction targeted for designs with large sparse multiplexers delivering up to 30% area reduction and resolved congestion.

“In the design services market that AAI serves, fast turnaround time and predictability are critical requirements for the RTL-to-GDSII flow,” said Bijan Kiani, Vice President of Marketing in Synopsys’ Design Group. “The advanced RTL congestion analysis, synthesis-based design-for-test and low power implementation, coupled with physical guidance to IC Compiler II, enable our customers to achieve faster turnaround times for their critical SoCs while achieving superior quality of results and predictable silicon success.”