400G hyperscale data centres with high performance Ethernet IP

The DesignWare 56G Ethernet PHY aims to deliver the best power and performance tradeoffs for the target application. To meet the bandwidth needs of leaf-spine architectures, the PHY supports single and aggregated link rates from 10 to 400G Ethernet, while meeting the PAM-4 and NRZ signalling. In addition, the PHY exceeds the performance requirements of OIF and IEEE standards for chip-to-chip, backplane, and copper/optical cable interfaces. The combination of Synopsys' 56G Ethernet PHY, digital controllers, verification IP, and source code test suites gives designers a complete Ethernet IP solution for their networking data centre systems.

For a more robust timing recovery and better jitter performance, the 56G Ethernet PHY receiver features a multi-loop clock and data recovery circuit, as well as a full-featured DSP. The unique architecture of the PAM-4 transmitter allows for precise feed forward equalisation to achieve channel performance requirements. The 56G Ethernet PHY's scalable architecture provides a foundation for next-gen 800G Ethernet applications requiring 112G connectivity.

John Koeter, vice president of marketing for IP at Synopsys, stated: "The growing amount of bandwidth required in the data centre is increasing the workload demand on the network infrastructure. Synopsys' DesignWare 56G Ethernet IP allows designers to meet the high-performance Ethernet connectivity requirements of 400G hyperscale data centre SoCs with less risk."

The silicon design kit for the DesignWare 56G Ethernet PHY in 16nm and seven nanometre FinFET processes are scheduled to be available in Q3 of 2018 and Q4 of 2018, respectively.