Design

28nm technology files enable efficient extraction

31st October 2016
Alice Matthews
0

It has been announced that Semiconductor Manufacturing International Corporation (SMIC) has adopted Synopsys' StarRC product as the standard solution for signoff parasitic extraction for its 28nm process technology. This standardisation is a result of a growing collaboration between SMIC and Synopsys to provide solutions to mutual customers to meet their increasing needs for accuracy, performance and efficiency at advanced nodes.

The StarRC solution delivered silicon-accurate extraction and productivity validated by SMIC for its 28nm process. The qualified StarRC technology files are available as the default in SMIC's 28nm Process Design Kits (PDKs) for both digital and custom designs.

"Continuing to build on the momentum of our 28nm process technology, a favorite node for semiconductor companies, is a priority for us, and the availability of qualified design tools is critical to support our expanding global customer base," said Anderson Huang, Senior Director of Technology Development at SMIC. "The partnership with Synopsys represents an enduring commitment to providing customers with the high-quality technologies and standards for use with our world-class manufacturing process. The deployment of StarRC in our 28nm PDKs bolsters the resources available to our mutual customers through StarRC's proven silicon accuracy and comprehensive capabilities for both digital and custom designs, allowing them to develop advanced designs with increased confidence and productivity." The StarRC product, an integral part of the Synopsys Galaxy Design Platform signoff solution, achieves high performance and efficiency with its scalable multi-core architecture, Simultaneous Multi-Corner (SMC) extraction and fast ECO capabilities, while maintaining industry-standard accuracy.

The StarRC product provides extraction capabilities across a wide range of applications, from 100+ million instance digital System-on-Chip (SoC) designs to custom memory, IP, standard cell and analogue designs. Integration with Synopsys IC Compiler II place and route and PrimeTime static timing analysis solutions allows designers to achieve even faster ECO design closure, while reducing disk space and processor core resources. In custom design environments, designers can cross-probe between parasitic and schematic views, annotate schematics with parasitics and perform visual debug. Significantly faster simulation runtimes and reduced disk space resources are realised through highly optimised extraction tuned for performance. The result of the collaboration between SMIC and Synopsys delivers qualified StarRC technology files in SMIC's 28nm PDK that enable mutual customers to use a silicon-accurate and efficient extraction solution for their designs targeting SMIC's 28nm node.

"Meeting customers' increasing needs to address complexity and accelerate design and analysis cycles are critical to propel them to silicon success at advanced process technologies," said Bijan Kiani, Vice President of Marketing for the Design Group at Synopsys. "SMIC's standardisation on StarRC for parasitic extraction for its 28nm process technology highlights the strong trust in our industry-leading technology to deliver on these important requirements and supports the innovations being driven by our mutual customers."

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