2- wire bus buffer now in full production

Using analog IC design principles for a digital bus, the IES5501 features low input-output offset voltages, allowing their use in a cascade or “daisy chain” fashion simplifying the engineers design process. With the low noise susceptibility and a wide allowable voltage range, the IES5501 makes it easier t ocreate larger bus networks without exceeding the maximum allowed bus capacitance for these types of bus.



The function of the IES5501 Bus Buffer is to extend the bus load limit by buffering the clock (SCL) and data (SDA) lines. The IES5501 finds its place in 2-wire bus systems within telecommunication systems (including ATCA), CompactPCI, VME bus systems, RAID products, power management systems, backplane management systems, bus switch/multiplexing buffering and for bus voltage level translation. The IES5501 significantly increases system noise margins on the intelligent platform management bus (IPMB) and are therefore excellent for implementing cost effective IPMB architectures.



The IES5501 bus buffer has superior switching times and input to output connection control is supported using the enable pin. The advanced analog design of the IES5501 enables easy level shifting of bus voltages, a wide range allowed between 1.8V and 15V. The application or removal of power to the device will not interfere with other bus activity.



The IES5501 is offered in 8-pin SO and 8-pin MSOP, all are RoHS compliant with samples available and is in full production.