Place & route solution enables ten times design throughput

The full-featured, production-ready netlist-to-GDSII implementation is claimed to provide the highest throughput and productivity for the best quality results. The IC Compiler II offers ultra-high capacity design planning, unique clock-building technology and advanced global analytical closure techniques, speeding up implementation runtime by five times, while using half the memory and half the iterations. Together, this enables ten times the design throughput. 

"Having worked closely with Synopsys since the early days of the IC Compiler II, we have been eagerly anticipating the 2014.12 release," commented Tatsuji Kagatani, Department Manager of Design Automation Department, Elemental Technology Development Division 1, Renesas System Design. "IC Compiler II delivered truly impressive turnaround time as well as good quality of results during the design activities of our latest MCU design in 40nm technology this year. We have come to view IC Compiler II as a key enabler of competitive differentiation, and are in the process of extending its application to all key in-flight programmes across 40-28nm and below technology nodes."

"Since our announcement of IC Compiler II earlier this year, customer response has been extremely positive, and the demand to gain access has been unprecedented. With broad availability of the 2014.12 release, we are well positioned to meet this growing demand," said Antun Domic, Executive Vice President and General Manager of the Design Group, Synopsys. "IC Compiler II is a landmark achievement that has been in the works for several years and is made possible by an asset mix unique to Synopsys – a deep and talented resource pool, diverse customer feedback by virtue of market leadership, and the ability to closely collaborate with some of the best, most advanced designers in the world."