Cadence Design Systems today advanced the design of giga-gate/gigahertz system on chips (SoCs) with a proven digital end-to-end flow at 28 nanometers that yields both performance and time-to-market advantages. Driven by the Cadence Silicon Realization approach, the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorith...

Cadence Design Systems today announced that Spreadtrum Communications (NASDAQ: SPRD), a leading provider of baseband and RF processor solutions for the wireless communications market headquartered in Shanghai, migrated to the Cadence® Silicon Realization flow and successfully taped out its first 40-nanometer low-power chip. The chip, a GSM/GPRS/EDGE/TD-SCDMA/HSPA mobile phone baseband, was taped out with one-pass silicon success.

Cadence Design Systems today introduced a qualified 32/28-nanometer reference flow targeting Common Platform technology. Cadence® collaborated closely with members of the Common Platform alliance—IBM, GLOBALFOUNDRIES, and Samsung Electronics—to develop a comprehensive flow from RTL synthesis to GDSII signoff for the advanced node, low-power high-k metal gate (HKMG) process technology.

Cadence today announced significant new advancements to help boost verification productivity for ASIC and FPGA designers. Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the 600-plus new capabilities expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.

Cadence Design Systems announce that the Cadence Virtuoso Accelerated Parallel Simulator has won the Elektra Electronics Industry Awards 2010 as the best design tool and development software. The Elektra Awards, established in 2003 and organized by Electronics Weekly and Reed Business Information in Europe, gives the industry an opportunity to recognize the achievements of individuals and companies across Europe.

Cadence Design Systems today announced that Semiconductor Manufacturing International Corporation (SMIC, NYSE: SMI and SEHK: 981), the largest semiconductor foundry in China, has adopted Cadence® Silicon Realization products for the design-for-manufacturing (DFM) and low-power technology at the core of SMIC’s 65-nanometer Reference Flow 4.1. Using Cadence Encounter Digital Implementation System as the foundation, the companies collaborated to ...

Cadence Design Systems today announced that Fujitsu Semiconductor Limited now supports the Cadence® C-to-Silicon Compiler for high-level synthesis in ASIC design flows. C-to-Silicon Compiler is the only high-level synthesis tool that embeds production RTL synthesis--Cadence Encounter® RTL Compiler--to generate implementation-ready RTL for the target application. This delivers a predictable flow from transaction-level model (TLM) to GDSII, with ...

Cadence Design Systems today announced that the company will be presenting a paper and showcasing its technology at RTI's 3D Architectures for Semiconductor Integration and Packaging conference. The conference will be Dec. 8 to 10 at the Hyatt Regency San Francisco Airport Hotel in Burlingame.

Cadence Design Systems (India) Pvt Ltd., a subsidiary of Cadence Design Systems, Inc. (NASDAQ: CDNS), announced that Open-Silicon, Inc., a leading semiconductor company focused on ASIC design, develop-to-spec, and derivative ICs, has successfully taped out a breakthrough high-performance processor at over 2.4GHz under typical conditions utilizing the Cadence® Silicon Realization product line. Open-Silicon completed the entire design using Cadenc...

Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, today introduced a new holistic approach to Silicon Realization that moves chip development beyond a patchwork of point tools to a streamlined end-to-end path of integrated technology, tools, and methodology. This approach represents a stark turn from the discrete and compartmentalized ways semiconductor and systems companies have traditionally achieved ...

Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, and Xilinx today introduced the new Xilinx IP Ecosystem microsite, a unified site meant to increase FPGA and ASIC designers’ visibility to the latest IP supporting the Xilinx programmable platform.. The microsite, developed as part of a broad initiative announced by Xilinx to transform and enable its ecosystem of third-party providers, is part of the C...

Cadence Design Systems today announced it is providing its customers an optimized implementation methodology for the new ARM® Cortex™-A15 MPCore™ processor that enables them to start designing Cortex-A15 processor-based SoCs immediately. As ARM developed the Cortex-A15 MPCore processor - its most advanced processor for mobile, consumer and infrastructure applications - Cadence® worked alongside the microprocessor IP leader to develop the me...

Cadence Design Systems today announced that Sunplus Technology Co., Ltd. (TAIEX: 2401, LSE: SUPD), a leading multimedia IC design company, adopted the Cadence Encounter® Digital Implementation (EDI) System for its multimedia system-on-chip (SoC) designs.

Cadence Design Systems today announced that the most advanced foundry in Mainland China, Semiconductor Manufacturing International Corporation (“SMIC”, NYSE: SMI and SEHK: 0981.HK), has adopted the Cadence Silicon Realization product line for advanced node, low-power designs. The Cadence Silicon Realization product line is composed of tools essential to turning designs into silicon. It is a key element of its EDA360 (the new Electronic Design...

Cadence Design Systems today announced that Global Unichip Corporation (GUC) has adopted the Cadence® Encounter® Timing System to reduce time to final design closure efficiently in its Encounter Digital Implementation (EDI) System-based design flows. By adopting the integrated signoff solution, GUC is able to shorten lead time and reduce tapeout schedule risk for Silicon Realization.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Global Unichip Corporation (GUC) has adopted Cadence® Virtuoso® custom design technologies to speed development of its high-speed interface IP. GUC also has adopted Cadence design for manufacturing (DFM) technologies for its advanced process node system-on-chip (SoC) designs.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Andes Technology, a Taiwanese provider of high-performance, low-power 32-bit processor IP and SoC platforms, has adopted the Cadence® digital front-end low-power design flow. The flow, based on the Common Power Format (CPF), deploys Cadence synthesis, simulation and formal verification technology. It enables Andes to provide its cus...

Cadence Design Systems, Inc. announced today that it will align product development to deliver on the EDA360 vision. The company will line up research and development (R&D) around the three core tenets of the vision: System Realization, SoC Realization and Silicon Realization.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Fujitsu Limited has adopted the Cadence® Encounter® Conformal® ECO Designer to cut costs and reduce design time in its engineering change order (ECO) implementation flow. The technology giant recently deployed the Cadence technology to tape out a network-control large-scale integration design of 40 million gates at a 65-nanometer ...

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced results for the second quarter of fiscal year 2010. Cadence reported second quarter 2010 revenue of $227 million, compared to revenue of $210 million reported for the same period in 2009. On a GAAP basis, Cadence recognized net income of $49 million, or $0.19 per share on a diluted basis, including $67 million in acquisition-related income tax benefit, in the second quarter of 2010, comp...