TSMC certifies Synopsys IC Compiler II

To support TSMC's 7-nm ultra-low voltage operation, key features such as parametric on chip variation (POCV) specified with Liberty Variation Format (LVF) and advanced waveform propagation (AWP) technologies are supported in the Galaxy Design Platform.

The platform is validated to handle the design rules and requirements of the full-colored 7-nm process, such as metal cut-awareness and reliability at all levels of the SoC design.

The 7-nm certification delivers routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE, and interoperable process design kits (iPDKs) for the 7-nm FinFET process.

"This collaboration effort with TSMC for the 7-nm technology node addresses the new process effect requirements by including IC Compiler II and other products from the Galaxy Design Platform," said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys.

"The collaboration allows our mutual customers to achieve quality results and faster time to market using the Galaxy Design Platform for their 7-nm designs."

"Building on our longstanding FinFET collaboration with Synopsys, this TSMC certification signifies that the tools from the Galaxy Design Platform are now ready for early engagements at 7-nm," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division.

The Galaxy tools included in TSMC's certification include:
• IC Compiler II place and route: Full color flow implementation with support for cut-metal, POCV and AWP;
• PrimeTime timing signoff solution: Ultra-low voltage support including POCV and AWP; 
• StarRC extraction: cut-metal and multi-patterning support; more stringent color-aware electromigration (EM) rules; 
• IC Validator physical verification: Certified runsets for signoff DRC and LVS; cut-metal and complex fill-to-signal space support;
• CustomSim reliability analysis solutions: Static and dynamic transistor-level analysis for color-aware EM rules support for analysis and IR-drop integrity;
• Custom Compiler full custom solution: Support for full coloring flow; track-pattern support, in-design EM/IR calculation and EM/IR analysis;
• HSPICE, CustomSim and FineSim simulation: Device modeling with self-heating effect and accuracy for analog, high-frequency and SRAM designs;
• NanoTime custom timing analysis: SPICE-accurate transistor-level static timing analysis for 7-nm devices;
• ESP-CV custom functional verification: Transistor-level symbolic equivalence checking for 7-nm SRAM, macros and library cell designs;
• In addition, color-aware EM rule support has been implemented in PrimeRail, and IR-drop enablement is actively ongoing.