Synopsys Collaborates with A*STAR IME to Optimize TSI Technology

efforts will lead to the demonstration of a heterogeneous 2.5D-IC design and manufacturing flow.

The electronic systems market is continually driving the demand for higher performance and functionality at lower cost. While traditional semiconductor technologies utilized in system-on-chip (SoC) devices continue to advance, the limitations in multi-chip systems, including interconnect density and inter-device bandwidth, are constraining system performance improvements. In addition, when multiple semiconductor technologies (such as MEMS, RF, analog and DRAM) are packaged independently from the system processor and related logic functions, it further impacts performance and cost. 3D-IC integration is an emerging solution for heterogeneous, multi-die and package systems. 2.5D-IC, a form of 3D-IC integration, combines silicon interposer, microbump and through-silicon via (TSV) technologies to enable the integration of heterogeneous, multi-die systems in a single package. In comparison to systems that contain the die packaged separately, 2.5D-IC offers many potential benefits, including higher system bandwidth, smaller form factor and faster time to product.



Collaborating with industry leaders is essential to our 2.5D/3D-IC research and development roadmap, said Professor Dim-Lee Kwong, executive director of IME. Through the consortium, a valuable resource sharing platform is formed where different fields of expertise and knowledge are readily available to optimize the research efforts and advance the market adoption of 2.5D integration for a wide range of applications.



Synopsys is a market leader in 3D-IC solutions. Examples of the 3D-IC solutions offered by Synopsys include Synopsys' Galaxy Implementation Platform and TCAD Sentaurus simulation software.



Synopsys' Galaxy platform features support the implementation and analysis of 2.5/3D-IC designs, including:



Physical Implementation



• IC Compiler™ multi-die physical implementation with support for placement, assignment and routing of microbumps and TSVs; inter-die alignment checks; redistribution layer (RDL) and signal routing, and power mesh creation on silicon interposer interconnection layers



Analysis and Signoff



• IC Validator design rule checking (DRC) and layout vs. schematic (LVS) connectivity checking between stacked die and silicon interposer



• StarRC™ Ultra parasitic extraction support for TSV, microbump, RDL and signal routing metal for TSI interconnection



• PrimeTime® static timing analysis of multi-die systems



Test



• DFTMAX™ compression for die-level design-for-test and multi-die test access infrastructure



• TetraMAX® ATPG for testing each die and test interconnection between dice on the silicon interposer



Synopsys' TCAD Sentaurus Interconnect supports the integration and optimization of 3D-IC fabrication and packaging by simulating TSV and microbump mechanical stress with its impact on the electrical performance of neighboring transistors and the reliability of the 3D-IC stack.

2.5D- and 3D-IC integration technologies are extending the lifespan of established semiconductor processes, said John Chilton, senior vice president of marketing and strategic development at Synopsys. They offer many potential benefits, including higher performance and lower power in a cost-effective system-level solution. IME's commitment to drive the realization of 3D-IC benefits and their deep research and development capabilities make them a great partner for Synopsys. We expect our joint collaboration as part of the TSI Consortium will enable designers to quickly create innovative heterogeneous multi-die systems using TSI technology.