Synopsys VC Formal selected for property verification

Through its native integration with VCS, Verdi and Certitude technologies, VC Formal also enabled Kyocera to build a highly efficient and robust formal verification methodology. "Kyocera designs complex SoCs to provide industry-leading printing solutions," said Motohide Murao, General Manager of Software 1 R&D Division at Kyocera Document Solution Inc.

"To efficiently perform comprehensive verification of these complex SoCs, static, dynamic and formal verification is required. With VC Formal and Certitude's fault injection and mutation technology, we addressed a potential problem for a specific bus access timing scenario in our past MFP products". "

By using a CPU model that could synthesise the logic with VC Formal, we also proved that the issue would not occur under the use conditions of the product. This enabled us to enhance the verification quality of our products and shorten time to market."

Synopsys VC Formal delivers faster property convergence through a set of unique engines and smart engine orchestration. Its innovative, high-capacity word-level data model enables formal apps to run on large SoCs, where traditional formal products fail.

VC Formal's native debug with Verdi enables simulation experts to quickly leverage formal technologies for faster verification closure. Additionally, unified compile with VCS accelerates creation of VC Formal setup from a simulation environment, reducing valuable time to market.

Through its integrated flow with Certitude, users can also apply fault injection techniques to identify and eliminate any gaps in formal verification testbench, eliminating bug escapes altogether.

"We have long collaborated with Kyocera on the delivery of advanced verification solutions for their multi-function printers," said Mo Movahed, vice president of R&D in the Synopsys Verification Group. "We are committed to providing the fastest, high capacity, formal verification solution that can scale with the growing complexity and shorter time-to-market of modern SoC designs."