Synopsys Custom Design Solution Enables Moortec Semiconductor to Tape Out High-performance Analog IP

With shrinking silicon geometries, there is a growing need for on-chip temperature monitoring to increase IC longevity and optimize performance. It is important for us to quickly and reliably develop our temperature sensor IP across multiple process nodes to meet the increased demand, said Stephen Crosher, managing director of Moortec Semiconductor. We chose Synopsys' custom solution because its advanced capabilities and streamlined integration provides the productivity and performance that our engineers need to quickly design and port the IP between 65-nanometer, 40-nanometer and 28-nanometer nodes while maintaining the accuracy and integrity of the design.
Moortec Semiconductor's latest temperature sensor IP blocks were designed using standard logic processes for 65-nanometer (nm), 40-nm and 28-nm geometries and can be easily instantiated multiple times across systems-on-chips (SoCs) for temperature profiling. Moortec used Synopsys' Custom Designer solution to complete the schematic design and layout for custom analog blocks, the HSPICE circuit simulator for pre-layout simulations and the CustomSim FastSPICE simulator to verify the extracted netlists from the StarRC extraction tool. The design was successfully taped out after final verification signoff with IC Validator for DRC and LVS.
Synopsys' custom solution continues to build momentum both in terms of customer adoption and technology innovation due to its open environment, integration within the Galaxy Implementation Platform and foundry iPDK support, said Bijan Kiani, vice president of product marketing at Synopsys. Customers like Moortec Semiconductor are realizing higher productivity in creating complex analog designs at advanced geometries by adopting Synopsys' unified solution for analog and mixed-signal design.