Synopsys and Actel renew OEM relationship for FPGA design software

“Actel’s customers have come to expect the best in FPGA synthesis over the years,” said Jim Davis, Vice President of Software and Systems Engineering at Actel. “Synopsys is a valued, best-in-class supplier, and we are very pleased to be able to continue to bundle Synopsys products as part of the Libero IDE.”

“Actel provides distinctive programmable solutions for important electronic applications, including those requiring low-power, radiation-tolerant or mixed-signal FPGAs,” said George Zafiropoulos, Vice President of Solutions Marketing at Synopsys. “Our technology leading FPGA design and verification tools have been designed to take full advantage of the unique features of Actel devices and to provide our mutual customers with the quality of results and productivity required to address the needs of their markets.”

In addition to the technology leading Synplify Pro FPGA synthesis product, the OEM agreement includes Synopsys’ Identify RTL debugger software. The Identify product is a functional verification tool that provides probing and visibility into a live, running FPGA. The Identify RTL Debugger allows designers to debug an operating FPGA directly in their RTL source code, providing an efficient alternative to debugging at the gate level, where signal names may have been changed by synthesis and no longer match the RTL.

Designers implementing DSP algorithms will have a very fast and reliable path into Actel devices using Synopsys’ Synplify DSP algorithm synthesis product. The Synplify DSP tool provides a unique high level synthesis methodology that realises significant productivity and optimisation advantages over traditional HDL design flows. System and algorithm designers can quickly capture complex algorithmic behaviour using the Synplify DSP model library, which includes vector arithmetic, fixed-point precision up to 128-bits, and a rich set of IP cores. The Synplify DSP synthesis engine allows designers to automatically implement and explore a range of area/speed-optimised architectures from a single model and generate verification testbenches from a high-level environment.