Sentaurus TCAD model for NBTI reliability simulation

NBTI has become more critical with the introduction of high-k metal gate (HKMG) processes and is a dominant reliability concern for FinFET, nanowire FET and future devices, contributing to the degradation of the threshold voltage, drain current, and other electrical parameters. The Sentaurus TCAD model enables manufacturers of advanced silicon processes working in advanced nodes to assess and mitigate NBTI degradation as part of transistor design and process definition.

"Our research over the years identified and characterised the underlying physical mechanism responsible for NBTI and helped create a framework for predictive DC and AC NBTI simulation of planar FETs," said Professor Souvik Mahapatra of IIT Bombay. "Working together with Synopsys, we have extended the model in Sentaurus TCAD for predictive NBTI simulation in FinFET and GAA nanowire FET. The model has been verified against hardware data, covers a wide range of experimental conditions, and has only three parameters for its calibration, making it suitable for practical TCAD simulations."

"Semiconductor manufacturers face many challenges in developing future process nodes due to the rising complexity of transistor architectures and fabrication processes," said Terry Ma, vice president of engineering for TCAD at Synopsys. "With this new NBTI model our customers can simulate NBTI degradation and minimise its impact through the optimisation of the transistor architecture in the early stages of technology development."