NetLogic Microsystems selects Synopsys as primary EDA partner

“Our continued success is driven by our leadership in technology innovation, our successful delivery of highly complex silicon products in advanced process nodes and our track record of first-silicon successes,” said Dr. Dimitrios Dimitrelis, vice president of engineering for NetLogic Microsystems. “The design tool efficiency, accuracy and robustness of Synopsys technology have helped us achieve this combination of product and technical excellence. We look forward to our continued collaboration with Synopsys as we develop next generation knowledge-based processors and physical layer products for advanced telecommunications, enterprise, data centre and storage networks.”

With this latest agreement, NetLogic Microsystems is consolidating on Synopsys’ Galaxy(TM) Implementation and Discovery(TM) Verification Platforms. The expanded set of selected products include Design Compiler(R) synthesis, PrimeTime(R) timing analysis and PrimeTime SI signal integrity analysis, Star-RCXT(TM) parasitic extraction, the VCS(R), ESP-CV, HSPICE(R) and HSIM(R) simulators for analogue and digital verification, NanoTime transistor-level static timing analysis, and DesignWare(R) Library’s portfolio of synthesisable and verification IP.

“Today’s economic realities require leading fabless companies to seek design partners who can help them reduce their total cost of design and accelerate the deployment of new designs implemented in the latest process technologies,” said John Chilton, senior vice president of marketing and business development at Synopsys. “By extending our collaboration with NetLogic Microsystems, we can leverage our mutual strengths and the efficiencies of a fully integrated Synopsys flow to help them deliver products that significantly enhance the performance and functionality of next generation networks.