Latest Innovations in Synopsys IC Compiler Deliver up to 40 Percent Power Reduction at HiSilicon

Device performance is our top priority, but in the green networking space, leading-edge performance with the lowest power is a key differentiator, said Yan-Qiu Diao, senior director, research and development, at HiSilicon Technologies Co., Ltd. IC Compiler's new final-stage leakage recovery capability delivered 40 to 50 percent standby power savings while preserving timing on blocks in our recently taped out designs. We have since deployed final-stage leakage recovery in our production tape-out flow.



Traditional methods for reducing leakage, the power consumed by ICs in idle or stand-by mode, have relied largely on multi-threshold libraries. New channel-length-biased cell libraries can effectively provide many variants of a given cell with the same functionality but different leakage power consumption. IC Compiler's latest release provides a powerful final-stage leakage recovery capability architected to manage a multitude of these leakage variants in order to substantially reduce stand-by power consumption while preserving timing. HiSilicon initially exercised this capability on a few trial blocks. Encouraged by more than 40 percent standby power savings coupled with very low impact on timing, they immediately applied this capability on several blocks of a live tape out and succeeded in substantially lowering their power consumption. This new capability is the latest addition to IC Compiler's comprehensive solution for advanced low-power designs.



Delivering capabilities that enable designers to stay at the forefront of the power-performance technology curve is a critical driver shaping every release of IC Compiler, said Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. As a key enabler of energy efficient equipment used in green networks, HiSilicon was pleased to recognize the improvements delivered by IC Compiler's final-stage leakage recovery.