IC Validator certified by Samsung

Synopsys In-Design technology also supports the runsets, which makes the same full-signoff accuracy checking available inside Synopsys' IC Compiler II physical implementation solution to deliver faster turnaround time and better timing results.

The Samsung-certified runsets, including design rule checking (DRC), layout-versus-schematic (LVS) and metal fill technology files, are available immediately from Samsung.

"As DRC complexity increases with each new advanced technology generation, designers continue to need highly predictable results and fast DRC signoff," said Jaehong Park, senior vice president of the Foundry Design Team at Samsung Electronics.

"Synopsys and Samsung Foundry have collaborated on an extensive IC Validator tool as well as runset qualification, and met all of the certification requirements. Our foundry customers can now use IC Validator's fast analysis in both In-Design and signoff flows to maximise power, performance and area benefits of Samsung Foundry's 10LPP process technology."

IC Validator, part of the Synopsys Digital Design Platform, is a comprehensive and highly scalable physical signoff solution including DRC, LVS, programmable electrical rule checks (ERC), dummy fill and DFM enhancement.

IC Validator is configured for today's extremely large designs by enabling both multi-threading and distributed processing over multiple machines to provide near linear runtime scalability benefits that extend to several hundreds of CPUs. IC Validator's massively parallel architecture utilises smart, memory-aware load scheduling and balancing technologies to maximise utilisation of mainstream hardware.

IC Validator is a companion product to IC Compiler II for In-Design physical signoff. In-Design allows place-and-route engineers to perform independent, timing-aware, signoff-quality analysis earlier―before the design is finalised and while correction can be automated.

In-Design technology enables new high-productivity functionality within the place-and-route environment, including automatic DRC repair, improved timing quality-of-results with timing-aware metal fill, and rapid ECO validation. In-Design physical verification eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.

"Manufacturing complexity at advanced nodes challenges designers to deliver within schedule," said Bijan Kiani, vice president of product marketing for the Design Group at Synopsys.

"Collaborating closely with leading foundries like Samsung ensures designers have timely access to performance optimised runsets. The runsets in concert with IC Validator's massively parallel architecture with near linear scalability provides our mutual customers the faster path to physical signoff closure."