Analysis
Fairchild Semiconductor Achieves First-Pass Silicon Success with DesignWare USB 2.0 nanoPHY IP
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Fairchild Semiconductor (Fairchild) has achieved first-pass silicon success for its FUSB2500 UTMI+ Low-Pin Interface (ULPI) USB On-The-Go (OTG) transceiver chip utilizing Synopsys' DesignWare® USB 2.0 nanoPHY IP.
FairTargeting the high-end handset market, the Fairchild FUSB2500 USB 2.0 OTG transceiver chip was an extremely complex design that would be their first 130 nanometer (nm) chip to be integrated by a major manufacturer. Fairchild acquired USB IP from Synopsys, an established IP provider, to allow them to focus on their product differentiation and meet their critical 14 month project schedule. Using Synopsys' DesignWare USB 2.0 nanoPHY IP enabled Fairchild to successfully launch their leading FUSB2500 transceiver chip into the market on schedule.
With a tight development schedule and complex design requirements, we wanted to partner with a trusted and established IP vendor such as Synopsys, said Jerry Johnston, senior director of switch and interface at Fairchild. The Synopsys' DesignWare USB 2.0 nanoPHY IP offered us a solution that would incorporate all of our design needs and meet our time-to-market window. Synopsys' DesignWare IP is a high-quality product and will continue to be a key element of our future product developments.
As companies such as Fairchild develop differentiated products that help their customers maintain a competitive edge, they can rely on Synopsys to help provide them with the necessary IP to meet their critical time-to-market window, said John Koeter, vice president of marketing for the Solutions Group at Synopsys. As a leading provider of USB IP, with over 2,000 design wins and millions of units shipping in volume, Synopsys invests heavily in developing high-quality DesignWare USB IP that delivers key functionality to address our customer's design requirements and reduce integration risk.