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“USB is a key connectivity choice for our customers and teaming-up with Evatronix allows us to give them best-in-class, cost-effective solutions,” said Ian Lankshear, Managing Director of EnSilica. “The Evatronix USB IP solutions, coupled with our eSi-Connect peripherals, offer our customers complete, ready-to-go eSi-RISC processor sub-systems that take the pain out of integrating hardware and software IP from different sources.”



EnSilica has integrated the Evatronix USB 1.1, 2.0 and 3.0 IP solutions, including support for USB OTG, into its eSi-SoC Generator tool, which automatically produces processor sub-system RTL including bus arbitration enabling USB SoC-based solutions to be rapidly generated for customers by EnSilica’s development team. Depending on customers’ system level requirements, support is provided for Low Speed, Full Speed, High Speed and SuperSpeed devices. The new SuperSpeed standard supports data rates up to 5Gb/s.



The Evatronix IP is highly configurable, allowing hardware resources to be optimized to the performance requirements of the end application. These include parameters like the number of end-points and options dedicated for USB DMA engine support. Suspend and resume power management functions are supported reducing the overall system power. A fully featured USB software stack, with Mass Storage Class option, provides everything required to deploy a low-cost USB processor sub-system reducing risk, cost and time to market for customers. The Evatronix range of USB IP is fully certified by the USB-IF.



In addition to the Evatronix USB IP, a rich set of eSi-Connect peripherals are available for integration with EnSilica’s eSi-RISC processors. They include cache and static memory interfaces through to peripherals such as I2C, UART, SPI, a Smartcard (ISO7816-3) interface, Ethernet, RTC, system timers, DMA and encryption accelerators.



“The partnership with EnSilica for high-end USB sub-systems secures our success especially in the performance-hungry USB 3.0 market,” said Carsten Elgert, VP Marketing and Sales at Evatronix. “Our customers get two top-end IP cores that work seamlessly together, and, most importantly, also save precious time on integration and testing, which is the key differentiating factor for developing profitable products in emerging markets.”



The eSi-SoC Generator supports either single or multi-processor architectures with a mixture of AMBA APB, AHB or AXI based buses. The SoC architecture and eSi-RISC processor configuration is described by an XML format file. Each eSi-RISC processor can be configured separately within the XML file with over 50 configuration options available for each processor. These include the base 16-bit or 32-bit data word support, memory architecture, addressing modes and extension instructions such as load multiple, bit field extraction, single cycle multiply and multi-cycle divide. This allows each processor to be optimized for the end application reducing silicon resources and minimizing the overall system power.