High purity waveforms, simply

A key requirement across a multitude of industries is to accurately produce, easily manipulate and quickly change waveforms of various frequencies and types. Whether a wideband transceiver requires an agile low-phase-noise frequency source with excellent spurious-free dynamic performance, or an industrial measurement and control system needs a stable frequency stimulus, the ability to quickly, easily and cost effectively generate an adjustable waveform while maintaining phase continuity is a critical design criterion that direct digital frequency synthesis can fulfil.



Often shortened to direct digital synthesis (DDS), the technique uses digital data processing to generate a frequency- and phase-tunable output related to a fixed frequency reference, or clock source, fc. In a DDS architecture, the reference or system clock frequency is divided down by the scaling factor, set by a programmable binary tuning word.



Stated simply, a direct digital frequency synthesiser translates a train of clock pulses into an analog waveform, typically a sine, triangular, or square wave. As Figure 1 shows, its essential parts are: a phase accumulator, which produces a number corresponding to a phase angle of the output waveform; a phase-to-digital converter, which generates the instantaneous digital fraction of the output amplitude occurring at a particular phase angle; and a D/A converter (DAC), which converts that digital value to a sampled analog data point.



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Figure 1. Functional block diagram of a DDS system



For sine-wave outputs, the phase-to-digital amplitude converter is usually a sine lookup table. The phase accumulator counts by N to generate a frequency; since changes to N result in immediate changes in the output phase and frequency the system is inherently phase-continuous, a critical attribute in many applications. No loop settling time is required, in contrast to analog-type systems, such as phase-locked-loops (PLLs).



The DAC is usually a high-performance circuit specifically designed to work with the DDS core (phase accumulator and phase-to-amplitude converter). In most cases, the resulting device, often a single chip, is commonly referred to as a complete DDS or C-DDS.



Practical DDS devices often integrate multiple registers to allow various frequency- and phase-modulation schemes to be realised. When included, the phase register’s contents are added after the phase accumulator. This enables the output sine wave to be phase-delayed in correspondence with a phase tuning word. This is extremely useful for phase-modulation applications in communication systems. The resolution of the adder circuit determines the number of bits in the phase tuning word and, therefore, the resolution of the delay.



Integrating a DDS engine and a DAC in a single device has advantages and disadvantages, but whether integrated or not, a DAC is required to create a high quality analog signal of exceptional purity. The DAC converts the digital sine output into an analog sine wave and may be either single-ended or differential (Figure 2). A few of the key requirements are low phase noise, excellent wide-band (WB-) and narrow-band (NB-) spurious-free dynamic range (SFDR), and low power consumption. If it is an external component, the DAC needs to be fast enough to process the signal—so devices with a parallel port are common.



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Figure 2: Typical DDS architecture and signal path with DAC



Alternative solutions



Other possibilities for frequency generation include analog phase-locked loops (PLLs), clock generators, and using an FPGA to dynamically program the output of a DAC. A simple comparison of the technologies can be made by examining spectral performance and power consumption, qualitatively demonstrated in Table 1.



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Table 1. DDS versus competing technologies—high level comparison



A phase-locked loop is a feedback loop comprising a phase comparator, a divider, and a voltage-controlled oscillator (VCO). The phase comparator compares a reference frequency with the output frequency (usually divided down by a factor, N), The error voltage generated by the phase comparator is applied to the VCO, which generates the output frequency. When the loop has settled, the output will bear an accurate relationship to the reference in frequency and/or phase. PLLs have long been recognised as superior devices for low phase noise and high spurious-free dynamic range (SFDR) applications requiring high fidelity and stable signals in a specific band of interest.



Their inability to accurately and quickly tune the frequency output and waveform and their slow response limits their suitability for applications such as agile frequency hopping and some frequency- and phase-shift keying applications.



Other approaches, including field-programmable gate arrays (FPGAs) with embedded DDS engines—in combination with off-the-shelf DACs to synthesise output sine waves—solve the frequency-hopping difficulties of PLLs, but have their own weaknesses. The main system disadvantages include higher operating and interface power requirements, higher cost, large size, and additional software-, hardware-, and memory overhead for the system developer. For example, up to 72kbytes of memory are required to generate a 10MHz output signal with 60dB dynamic range using the DDS engine option on modern FPGAs. In addition, the designer needs to be comfortable and familiar with subtle trade-offs and the architecture of the DDS core.



As a practical matter (Table 2), rapid advances in CMOS processing, together with modern digital design techniques and improved DAC topologies, have resulted in the DDS technology achieving power consumption, spectral performance, and cost levels that were previously unattainable for a wide range of applications. While complete DDS products will never match the highest performance and design flexibility achievable with custom combinations of high-end D/A converter technology and FPGAs, the size-, power- and cost benefits, coupled with the simplicity of DDS devices, may make them easily the first choice for many applications.



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Table 2. Benchmark Analysis Summary—Frequency-Generation Technologies (<50 MHz)



Also note that since a DDS device fundamentally embodies a digital method of generating an output waveform, it can simplify the architecture of some solutions or make it possible to digitally program the waveform. While a sine wave is normally used to explain the function and operation of a DDS, it is easily possible to generate triangular or square (clock) wave outputs from modern DDS ICs, avoiding the need for a lookup table in the former case, and for a DAC in the latter case, where the integration of a simple yet precise comparator will suffice.



Performance and limitations



The actual output of the DAC is not a continuous sine wave but a train of pulses with a sinusoidal time envelope. The corresponding frequency spectrum is a set of images and aliases. The images lie along a sin x/x envelope. Filtering is necessary to suppress frequencies outside the band of interest, but it cannot suppress higher-order aliases (due to DAC nonlinearities, for example) appearing within the pass band.



The Nyquist Criterion dictates that a minimum of two samples per cycle are required to reconstruct a desired output waveform; in typical DDS applications a low-pass filter is utilised to suppress the effects of the image responses in the output spectrum. To keep the cutoff requirements of the low-pass filter reasonable and the filter design simple, an accepted guideline is to limit the fOUT bandwidth to approximately 40% of the fCLOCK frequency using an economical low-pass output filter.



The amplitude of any given image in response to the fundamental can be calculated using the sin x/x formula. Because the function rolls off with frequency, the amplitude of the fundamental output will decrease inversely with its tuned frequency; in a DDS system, the decrease will be –3.92dB over the dc to Nyquist bandwidth.



The amplitude of any given image in response to the fundamental can be calculated using the sin x/x formula. Because the function rolls off with frequency, the amplitude of the fundamental output will decrease inversely with its tuned frequency; in a DDS system, the decrease will be –3.92dB over the dc to Nyquist bandwidth.



The amplitude of the first image is substantial—within 3 dB of the fundamental. To simplify filtering requirements for DDS applications, it is important to generate a frequency plan and analyse the spectral considerations of the image and sin x/x amplitude responses at the desired fOUT and fCLOCK frequencies. Online interactive design tools supporting the Analog Devices DDS product family allow for quick and easy simulation of where images lie and allow the user to choose frequencies where images are outside the band of interest.



Other anomalies in the output spectrum, such as integral and differential linearity errors of the DAC, glitch energy associated with the DAC, and clock feedthrough noise, will not follow the sin x/x roll-off response. These anomalies will appear as harmonics and spurious energy in many places in the output spectrum—but will generally be much lower in amplitude than the image responses. The general noise floor of a DDS device is determined by the cumulative combination of substrate noise, thermal noise effects, ground coupling, and other sources of signal coupling. The noise floor, performance spurs, and jitter of a DDS device are greatly influenced by circuit board layout, the quality of the power supplies, and—most importantly—the quality of the input reference clock.



Data encoding and synchronisation



From its exclusive origins in radar and military applications, some of the advances in DDS product characteristics (performance improvements, cost, and size) have combined to make DDS technology very popular in modulation and data encoding applications.



Binary frequency shift keying (BFSK, or simply FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier between one (binary 1, or mark) and the other (binary 0, or space) of two discrete frequencies. Figure 3 shows the relationship between the data and the transmitted signal.



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Figure 3: Binary FSK modulation



Binary 1s and 0s are represented as two different frequencies, f0 and f1, respectively. This encoding scheme is easily implemented with a DDS device. The DDS frequency tuning word representing the output frequencies is changed so that f0 and f1 are generated from 1s and 0s to be transmitted. In at least two members of Analog Devices’ complete-DDS product families (the AD9834 and the AD9838), the user can simply program the two current FSK frequency tuning words into the IC’s embedded frequency registers. To shift output frequency, a dedicated pin, FSELECT, selects the register containing the appropriate tuning word.



Phase-shift keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier remains constant, and the phase of the transmitted signal is varied to convey the information. Several schemes can be used to accomplish PSK. The simplest method, commonly known as binary PSK (or BPSK), uses only two signal phases: 0° (logic 1) and 180° (logic 0). The state of each bit is determined according to the state of the preceding bit. If the phase of the wave does not change, the signal state stays the same (low or high). If the phase of the wave changes by 180°, i.e., if the phase reverses—the signal state changes (low to high, or high to low). PSK encoding is easily implemented with a DDS product as most of the devices have a separate input register (a phase register) that can be loaded with a phase value. This value is directly added to the phase of the carrier without changing its frequency. Changing the contents of this register modulates the phase of the carrier, generating a PSK output. For applications that require high-speed modulation, the AD9834 and AD9838, which have pairs of phase registers, allow signals on a PSELECT pin to alternate between the preloaded phase registers to modulate the carrier as required.



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Figure 3: FSK encoding using the tuning-word selector of an AD9834 or AD9838 DSS



More complex forms of PSK employ four or eight wave phases. This allows binary data to be transmitted at a faster rate per phase change than is possible with BPSK modulation. In four-phase modulation (quadrature PSK), the possible phase angles are 0°, +90°, –90°, and +180°; each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow complex phase modulation schemes to be implemented by continuously updating different phase offsets to the registers.



I/Q Capability



Many applications require the generation of two or more sinusoidal or square wave signals having a known phase relationship. A popular example is in-phase and quadrature modulation (I/Q), a technique wherein signal information is derived from a carrier frequency at its 0° and 90° phase angles. Two single DDS components can be run from the same source clock to output signals whose phase relationship can be directly controlled and manipulated. In Figure 4, the AD9838 devices are programmed using one reference clock; the same RESET pin is used to update both devices. In this way, simple I/Q modulation can be achieved.



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Figure 4: Synchronising two DDS components



A reset must be initiated after power-up and before transferring any data to the DDS. This establishes the DDS output in a known phase, which becomes the common reference angle that allows synchronisation of multiple DDS devices. When new data is sent simultaneously to multiple DDS devices, a coherent phase relationship can be maintained—or the relative phase offset between multiple DDS devices can be predictably shifted by means of the phase offset register. The AD983x series of DDS products have 12 bits of phase resolution, providing an effective resolution of 0.1°.



Network Analysis



DDS can be highly useful for digitally controlling stimulus frequency and phase, such as network analysis. This could be anywhere there is a basic requirement to generate frequency-based signals and compare phase and amplitude of the response signal(s) to the original signal, or if a range of frequencies needs to be excited through the system, or if test signals with different phase relationships (as in systems with I/Q capability) are required.



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