Protocol exerciser/analyser tests PCI Express 4.0 designs

9th October 2015

Mick Elliott

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Datasheet

A PCI Express (PCIe) protocol exerciser/analyser for testing PCI Express 4.0 designs and products has been introduced by Teledyne LeCroy. The Summit Z416 exerciser/analyser addresses the needs of PCI Express developers by providing high performance 16GT/s traffic generation on devices with link widths up to 16 lanes. In addition to traffic generation, protocol analysis featuring Teledyne LeCroy’s industry-standard CATC Trace and other traffic displays and data reports are available.

The Summit Z416 supports exerciser functions that can be used for traffic generation and device/host emulation, as well as providing the industry a platform for development of standardized compliance test suites. Additionally, the support error injection functions to enable developers to test error recovery routines important to reliable interoperability of PCIe 4.0 products.

Along with the exerciser/analyser, a PCIe 4.0 test platform, PCIe 4.0 Verification Load Board (VLB) and PCIe 4.0 Verification Base Board (VBB) will be released to form a complete suite of protocol test tools for all developers working on or interested in PCI Express 4.0 products.

“Designers implementing the PCIe 4.0 specification’s fast 16 GT/s data rates in high-performance enterprise systems require a full-featured protocol test system,” said Scott Knowlton, Sr. Product Marketing Manager, Synopsys. “The combination of Synopsys’ DesignWare IP for PCIe 4.0 and test systems like Teledyne LeCroy’s Summit Z416 enables our mutual customers to design their SoCs more efficiently, analyse and test their silicon thoroughly and bring their solutions to the market quickly.”

Protocol analysers and exercisers are key tools to help driver and firmware developers understand serial data communication between their devices and systems. The Summit Z416 features a unified single application that incorporates traffic generation and protocol analysis. A protocol exerciser is an important part of protocol development and specification corner case testing.

It provides realistic traffic to devices under test and can also emulate complex host- or device-side traffic while the protocol analyser acquires, records, decodes, analyses and displays complex high-speed PCI Express I/O streams.

Users will have access to analysis and reporting capabilities that are highly utilised in the PCIe industry. When analysers and exercisers are used together developers can create powerful script level traffic and monitor the results of all tests.