Real-time compliance analyser for DDR4, DDR3, DDR3L memory

It provides instantaneous observability of memory interfaces over long periods of time, providing deep insight into memory bus activity that can help to shorten debug cycles and speed time to market. As the industry transitions to new memory technologies like DDR4 and DDR3L with higher data rate, lower power consumption and greater capacity, designers face new challenges to validate and debug devices with tighter margins, faster edge rates and complex bus protocols.

The analyser features a dual architecture that enables the detection of protocol violations coupled with the ability to acquire and analyse violations and determine bus performance. It has an integrated protocol analyser that monitors a DDR memory bus at-speed, reporting statistical results on events and violations in real-time. It also has an integrated, full function logic analyser with 1G cycle acquisition depth.

The instrument incorporates a fully programmable front-end that provides the ability to generate oscilloscope-like eye diagrams to graphically illustrate DDR PHY settings, bus integrity and required sample points. The Tektronix family of probes and interposers are shared between Tektronix 7000 series logic analysers and the MCA4000, providing the ability to view high speed timing, state, protocol and real-time analysis data simultaneously with one single load.