Signal quality analyser-R measures FEC symbol errors

With the new ED module, the MP1900A is the first BERT to support real-time measurement of FEC symbol errors, providing design engineers a single-instrument solution to more efficiently evaluate next-generation 400 and 800GbE high-speed devices and transceivers. 

The new PAM ED features input-sensitivity performance, as well as the real-time capability to detect FEC symbol errors based on the 400GbE FEC standard. In addition to conventional bit error rate (BER) measurement, the MP1900A also supports jitter tolerance measurements for assessing error correction capability using FEC, as required by transmissions using high-speed PAM4 signals.

For the first time, engineers can monitor changes in bit errors and FEC symbol errors with changes in input amplitude and jitter conditions in real-time with the MP1900A. The result is engineers can quickly and reproducibly evaluate when symbol error counts exceed the correction ability of FEC. Since the new FEC analysis function is compatible with conventional jitter tolerance automatic measurement software, the MP1900A BERT supports one-button jitter tolerance measurements based on whether error correction using FEC is possible.

Anritsu addresses an emerging market need with the new FEC analysis function of the MP1900A. Evaluation of devices and transceivers supporting PAM4 not only requires jitter tolerance and sensitivity evaluations based on conventional bit error and error-free measurements, but also measurement of error correction using FEC. The MP1900A, with the new PAM4 ED module, satisfies these testing parameters. 

MP1900A BERT Outline

The Signal Quality Analyser-R MP1900A series consists of multichannel bit error rate (BER) measuring instruments. The modular BERTs can inspect and verify next-generation network interfaces, such as 400 GbE and 800 GbE, as well as high-speed bus interfaces, such as PCI Express 4.0/5.0/6.0, USB3.2, USB4, and Thunderbolt. In addition to more accurate BER measurements, the MP1900A helps shorten development times for high-speed devices and transceivers.